Description
The DSP1627 is Lucent Technologies Microelectronics Group first digital signal processor offering 100 MIPS operation at 3.0 V and 80 MIPS operation at 2.7 V with a reduction in power consumption. Designed specifically for applications requiring low power dissipation in digital cellular systems, the DSP1627 is a signal-coding device that can be programmed to perform a wide variety of fixed-point signal processing functions. The device is based on the DSP1600 core with a bit manipulation unit for enhanced signal coding efficiency. The DSP1627 includes a mix of peripherals specifically intended to support processingintensive but cost-sensitive applications in the area of digital wireless communications.

FEATUREs
■ Optimized for digital cellular applications with a bit manipulation unit for higher coding efficiency.
■ On-chip, programmable, PLL clock synthesizer.
■ 14 ns and 11 ns instruction cycle times at 5 V, 10 ns instruction cycle time at 3.0 V, and 20 ns and 12.5 ns instruction cycle times at 2.7 V, respectively.
■ Mask-programmable memory map option: The DSP1627x36 features 36 Kwords on-chip ROM. The DSP1627x32 features 32 Kwords on-chip ROM and access to 16 Kwords external ROM in the same map. Both feature 6 Kwords on-chip, dual-port RAM and a secure option for on-chip ROM.
■ Low power consumption:
    — <5.5 mW/MIPS typical at 5 V.
    — <1.5 mW/MIPS typical at 2.7 V.
■ Flexible power management modes:
    — Standard sleep: 0.5 mW/MIPS at 5 V. 0.12 mW/MIPS at 2.7 V.
    — Sleep with slow internal clock: 1.4 mW at 5 V. 0.4 mW at 2.7 V.
    — Hardware STOP (pin halts DSP): <20 µA.
■ Mask-programmable clock options: crystal oscillator, small signal, and CMOS.
■ Low-profile TQFP package (1.5 mm) available.
■ Sequenced accesses to X and Y external memory.
■ Object code compatible with the DSP1617.
■ Single-cycle squaring.
■ 16 x 16-bit multiplication and 36-bit accumulation in one instruction cycle.
■ Instruction cache for high-speed, program-efficient, zerooverhead looping.
■ Dual 25 Mbits/s serial I/O ports with multiprocessor capability—16-bit data channel, 8-bit protocol channel.
■ 8-bit parallel host interface:
    — Supports 8- or 16-bit transfers.
    — Motorola* or Intel † compatible.
■ 8-bit control I/O interface.
■ 256 memory-mapped I/O ports.
■ IEEE‡ P1149.1 test port (JTAG boundary scan).
■ Full-speed in-circuit emulation hardware development system on-chip.
■ Supported by DSP1627 software and hardware development tools.