Functional Description[1]
The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

FEATUREs
• Supports 133 MHz bus operations
• 2M x 36/4M x 18/1M x 72 common IO
• 3.3V core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
    — 6.5 ns (133 MHz version)
• Provide high-performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1481V33, CY7C1483V33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1487V33 available in Pb-free and non-Pb-free 209 ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option