Functional Description[1]
The CY7C1348G SRAM integrates 128K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

FEATUREs
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
   — Depth expansion without wait state
• 128K × 36 common I/O architecture
• 3.3V core power supply (VDD)
• 3.3V/2.5V I/O power supply (VDDQ)
• Fast clock-to-output times
   — 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in lead-free 100-Pin TQFP package
• “ZZ” Sleep Mode option