[Silicon Laboratories]

System Overview
The C8051F12x and C8051F13x device families are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (100-pin TQFP) or 32 digital I/O pins (64-pin TQFP).

Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.

• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (100 MIPS or 50 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 12 or 10-bit 100 ksps ADC with PGA and 8-channel analog multiplexer
• True 8-bit 500 ksps ADC with PGA and 8-channel analog multiplexer (C8051F12x Family)
• Two 12-bit DACs with programmable update scheduling (C8051F12x Family)
• 2-cycle 16 by 16 Multiply and Accumulate Engine (C8051F120/1/2/3 and C8051F130/1/2/3)
• 128 or 64 kB of in-system programmable Flash memory
• 8448 (8 k + 256) bytes of on-chip RAM
• External Data Memory Interface with 64 kB address space
• SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with 6 capture/compare modules
• On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor