OVERVIEW
The BCM5703 is a fully integrated 10/100/1000BASE-T Gigabit Ethernet media access control and physical layer transceiver solution for high performance network applications. The BCM5703 is a highly integrated solution combining a triple-speed, IEEE 802.3 compliant media access controller (MAC), PCI and PCI-X bus interfaces, an onchip buffer memory, and an integrated physical layer transceiver in a single device. The BCM5703 is fabricated in a low-voltage, 0.13-µm CMOS process providing a low-power system solution. The BCM5703 provides a complete single-chip Gigabit Ethernet NIC or LOM solution.
• Single-chip solution for LAN on Motherboard (LOM) and network interface card (NIC) applications
• Integrated 10BASE-T/100BASE-TX/1000BASE-T transceivers
• 10/100/1000 triple-speed MAC
• Host interfaces
- PCI v2.2—32/64 bits, 33/66 MHz
- PCI-X v1.0—64 bits, 66/100/133 MHz
• Ultra-deep 96-KB on-chip packet buffer
• Dual high-speed RISC cores with 16-KB caches
- Programmable, in-line packet classification
• SMBus 2.0 controller
• On-chip power circuit controller and Wake on LAN (WOL) power switching circuit
• Performance features:
• TCP, IP, UDP checksum
• TCP segmentation
• CPU task offload
• Adaptive interrupts
• Ultra-deep 96-KB packet buffer
• Robust manageability:
• PXE 2.0 remote boot
• Alert Standard Format—ASF 1.0 support
• Wake on LAN
• Out-of-box (OOB) Wake on LAN
• Intelligent platform management interface (IPMI), version 1.5
• Statistic gathering (SNMP MIB II, Ethernet-like MIB, Ethernet MIB)
• Comprehensive diagnostic and configuration software suite
• ACPI 1.1a compliant multiple power modes
• Advanced network features:
• Priority queuing—802.1p layer 2 priority encoding; support for four priority queues
• Virtual LANs—802.1q VLAN tagging; support for up to 64 VLANs
• Jumbo frames (9 KB)
• 802.3x flow control
• Advanced server features:
• Link aggregation—802.3ad, GEC/FEC, Smart Load Balancing™ (supports heterogeneous teams)
• Heterogeneous, mixed-speed failover
• PCI Hot-Plug support
• Low-power, 0.13-um CMOS design
• 400-pin FBGA package
• 3.3V I/Os (5V tolerant)
• JTAG