Description
The AT49BV16X4(T) is 2.7 to 3.6 volt 16-megabit Flash memory organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 40 blocks for erase operations. The device is offered in 48-pin TSOP and 48-ball µBGA packages. The device has CE, and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single 2.7V power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector. Once the data protection for a given sector is enabled, the data in that sector cannot be changed using input levels between ground and VCC.
The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice versa. This operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend feature. This feature will put the Erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. There is no reason to suspend the erase operation if the data to be read is in the other memory plane. The end of a program or an Erase cycle is detected by the Ready/Busy pin, Data polling, or by the toggle bit.
A VPP pin is provided to improve program/erase times at lower supply voltages. This pin does not need to be utilized. If it is not used the pin should be connected to ground or VCC. To take advantage of faster programming, the pin should supply 5.0 volts during program and erase operations.

FEATUREs
• 2.7V to 3.6V Read/Write
• Access Time - 90 ns
• Sector Erase Architecture
   – Thirty 32K word (64K byte) Sectors with Individual Write Lockout
   – Eight 4K word (8K byte) Sectors with Individual Write Lockout
   – Two 16K word (32K byte) Sectors with Individual Write Lockout
• Fast Word Program Time - 20 µs
• Fast Sector Erase Time - 200 ms
• Dual Plane Organization, Permitting Concurrent Read while Program/Erase
   – Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
   – Memory Plane B: Twenty-Four 32K Word Sectors
• Erase Suspend Capability
   – Supports Reading/Programming Data from Any Sector by Suspending Erase of
      Any Different Sector
• Low Power Operation
   – 25 mA Active
   – 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• Optional VPP Pin for Fast Programming
• RESET Input for Device Initialization
• Sector Program Unlock Command
• TSOP, CBGA, and µBGA Package Options
• Top or Bottom Boot Block Configuration Available