GENERAL DESCRIPTION
The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize line card performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
   Fully integrated VCO/PLL core
   0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz
   0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
   0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz
   0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz
   Input crystal frequency of 19.44 MHz, 25 MHz, or
      25.78125 MHz
   Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,
      100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,
      159.375 MHz, 161.13 MHz, and 312.5 MHz outputs
   LVDS/LVPECL/LVCMOS output format
   Integrated loop filter
   Space saving 4.4 mm × 5.0 mm TSSOP
   100 mW power dissipation (LVDS output)
   120 mW power dissipation (LVPECL output)
   3.3 V operation

APPLICATIONS
   GbE/FC/SONET line cards, switches, and routers
   CPU/PCI-e applications
   Low jitter, low phase noise clock generation