General Description
The A29800A is an 8Mbit, 5.0 volt-only Flash memory organized as 1,048,576 bytes of 8 bits or 524,288 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The is offered in 48-ball FBGA and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29800A can also be programmed in standard EPROM programmers.
The A29800A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29800A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29800A also offers the ability to program in the Erase Suspend mode. The standard A29800A offers access time of 55ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable (OE ) controls.

FEATUREs
■ Single power supply operation
   - Full voltage range: 4.5 to 5.5 volt for read and write operations
■ Access time:
   - 55ns (max.)
■ Current:
   - 20 mA typical active read current
   - 30 mA typical program/erase current
   - 6μA typical CMOS standby
■ Flexible sector architecture
   - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
   - 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
   - Any combination of sectors can be erased
   - Supports full chip erase
   - Sector protection:
      A hardware method of protecting sectors to prevent any
      inadvertent program or erase operations within that
      sector. Temporary Sector Unprotect feature allows code
      changes in previously locked sectors
■ Industrial operating temperature range: -40ºC to +85ºC for
   -U series
■ Unlock Bypass Program Command
   - Reduces overall programming time when issuing multiple program command sequence
■ Top or bottom boot block configurations available
■ Embedded Algorithms
   - Embedded Erase algorithm will automatically erase the
      entire chip or any combination of designated sectors and
      verify the erased sectors
   - Embedded Program algorithm automatically writes and
      verifies data at specified addresses
■ Minimum 100,000 program/erase cycles per sector
■ 20-year data retention at 125ºC
   - Reliable operation for the life of the system
■ Compatible with JEDEC-standards
   - Pinout and software compatible with single-power-supply
      Flash memory standard
   - Superior inadvertent write protection
■ Data Polling and toggle bits
   - Provides a software method of detecting completion of
      program or erase operations
■ Ready / BUSY pin (RY / BY )
   - Provides a hardware method of detecting completion of
      program or erase operations
■ Erase Suspend/Erase Resume
   - Suspends a sector erase operation to read data from, or
      program data to, a non-erasing sector, then resumes the
      erase operation
■ Hardware reset pin (RESET )
   - Hardware method to reset the device to reading array data
■ Package options
   - 48-pin TSOP (I) or 48-ball TFBGA
   - All Pb-free (Lead-free) products are RoHS2.0 compliant