The Intel® 440BX AGPset is intended for the Pentium® II processor platform and emerging 3D graphics/multimedia applications. The 82443BX Host Bridge provides a Host-to-PCI bridge, optimized DRAM controller and data path, and an Accelerated Graphic Port (AGP) interface. AGP is a high performance, component level interconnect targeted at 3D graphics applications and is based on a set of performance enhancements to PCI.
The I/O subsystem portion of the Intel® 440BX AGPset platform is based on the 82371EB (PIIX4E), a highly integrated version of the Intel’s PCI-ISA bridge family. The Intel® 440BX AGPset is ideal for the Mobile AGPset Pentium II processor platforms; providing full support for all system suspend modes and segmented power planes.

Intel 82443BX Features
• Processor/host bus support
   — Optimized for Pentium® II processor at 100 MHz system bus frequency; Support for 66 MHz
   — Supports full symmetric Multiprocessor (SMP) Protocol for up to two processors; I/O APIC related buffer management support (WSC# signal)
   — In-order transaction and dynamic deferred transaction support
   — Desktop optimized GTL+ bus driver technology (gated GTL+ receivers for reduced power)
• Integrated DRAM controller
   — 8 to 512 Mbytes or 1GB (with registered DIMMs)
   — Supports up to 4 double-sided DIMMs (8 rows memory)
   — 64-bit data interface with ECC support (SDRAM only)
   — Unbuffered and Registered SDRAM (Synchronous) DRAM Support (x-1-1-1 access @ 66 MHz, x-1-1-1 access @ 100 MHz)
   — Enhanced SDRAM Open Page Architecture Support for 16- and 64-Mbit DRAM devices with 2k, 4k and 8k page sizes
• PCI bus interface
   — PCI Rev. 2.1, 3.3V and 5V, 33MHz interface compliant
   — PCI Parity Generation Support
   — Data streaming support from PCI to DRAM
   — Delayed Transaction support for PCI-DRAM Reads
   — Supports concurrent CPU, AGP and PCI transactions to main memory
• AGP interface
   — Supports single AGP compliant device (AGP-66/133 3.3V device)
   — AGP Specification Rev 1.0 compliant
   — AGP-data/transaction flow optimized arbitration mechanism
   — AGP side-band interface for efficient request pipelining without interfering with the data streams
   — AGP-specific data buffering
   — Supports concurrent CPU, AGP and PCI transactions to main memory
   — AGP high-priority transactions (“expedite”) support
• Power Management Functions
   — Stop Clock Grant and Halt special cycle translation (host to PCI Bus)
   — Mobile and “Deep Green” Desktop support for system suspend/resume (i.e., DRAM and power-on suspend)
   — Dynamic power down of idle DRAM rows
   — SDRAM self-refresh power down support in suspend mode
   — Independent, internal dynamic clock gating reduces average power dissipation
   — Static STOP CLOCK support
   — Power-on Suspend mode
   — Suspend to DRAM
   — ACPI compliant power management
• Packaging/Voltage
   — 492 Pin BGA
   — 3.3V core and mixed 3.3V and GTL I/O
• Supporting I/O Bridge
   — System Management Bus (SMB) with support for DIMM Serial Presence Detect (SPD)
   — PCI-ISA Bridge (PIIX4E)
   — Power Management Support
   — 3.3V core and mixed 5V, 3.3V I/O and interface to the 2.5V CPU signals via open-drain output buffers