MCP FEATURES
• Power supply voltage of 2.7 to 3.1 volt
• High performance:
   - Flash access time as fast as 70 ns
   - PSRAM access time as fast as 80 ns
• Package: 65-Ball FBGA
• Operating Temperature: –30°C to +85°C

FLASH MEMORY FEATURES
• 0.16 µm Process Technology
• Simultaneous Read/Write Operations (Dual Bank)
• FlexBankTM architecture
   - Bank A : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
   - Bank B : 24 Mbit (64 KB x 48)
   - Bank C : 24 Mbit (64 KB x 48)
   - Bank D : 8 Mbit ( 8 KB x 8 and 64 KB x 15)
   - Two virtual Banks are chosen from the combination
      of four physical banks (Refer to "Example of Virtual
      Banks Combination Table" and Simultaneous
      Operation Table" in FLEXIBLE SECTOR-ERASE
      ARCHITECTURE on FLASH MEMORY)
   - Host system can program or erase in one bank, and
      then read immediately and simultaneously from the
      other bank with zero latency between read and write
      operations.
   - Read-while-erase
   - Read-while-program
• Single 3.0 V Read, Program, and Erase
   - Minimized system level power requirements
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
   - Sixteen 4 Kword and one hundred twenty-six 32
      Kword sectors in word
   - Any combination of sectors can be concurrently
      erased
   - Supports full chip erase
• Hidden ROM (Hi-ROM) Region
   - 256 byte of Hi-ROM, accessible through a new "HIROM Enable" command sequence
   - Factory serialized and protected to provide a secure
   electronic serial number (ESN)
• WP/ACC Input Pin
   - At VIL, allows protection of “outermost” 2 × 8 Kbytes
      on both ends of boot sectors, regardless of sector
      protection/unprotection status
   - At VIH, allows removal of boot sector protection
   - At VACC, program time will be reduced by 40 %