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74ACT1284MSAX データシート - Fairchild Semiconductor

74ACT1284MSA image

部品番号
74ACT1284MSAX

コンポーネント説明

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Fairchild
Fairchild Semiconductor Fairchild

General Description
The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port mode (ECP).
The HD (active HIGH) input pin enables the B Ports to switch from open Drain to a high drive totem pole output, capable of sourcing 14 mA on all seven buffers. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (active HIGH) enables data flow from A Ports to B Ports. DIR (active LOW) enables data flow from B Ports to A Ports.


FEATUREs
■ TTL-compatible inputs
■ A Ports have standard 4 mA totem pole outputs
■ Typical input hysteresis of 0.5V
■ B Port high drive source/sink capability of 14 mA
■ Bidirectional non-inverting buffers
■ Supports IEEE P1284 Level 1 and Level 2 signaling
   standards for bidirectional parallel communications
   between personal computers and printing peripherals
■ B Port outputs in High Impedance mode during power down
■ Guaranteed 4000V minimum ESD protection


部品番号
コンポーネント説明
PDF
メーカー
IEEE 1284 Transceiver
Fairchild Semiconductor
IEEE 1284 Transceiver
Fairchild Semiconductor
IEEE 1284 Transceiver
Fairchild Semiconductor
IEEE 1284-Compatible Parallel Interface
Intel
IEEE-1284 to USB Bridge
Genesys Logic
IEEE 1284 ECP/EPP Termination Network
California Micro Devices => Onsemi
IEEE 1284 ECP/EPP Termination Network
California Micro Devices Corp
P/ACTIVE™ IEEE 1284 ECP/EPP TERMINATION NETWORK
California Micro Devices => Onsemi
P/Acitve™ IEEE 1284 ECP/EPP Termination Network
California Micro Devices Corp
P/ACTIVE™ IEEE 1284 ECP/EPP TERMINATION NETWORK
California Micro Devices Corp

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