ADSP-2183KCA-210 データシートの表示（PDF） - Analog Devices

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ADSP-2183KCA-210

DSP Microcomputer

Analog Devices 

ADSP-2183

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24 or 32 word, time-division multiplexed,

serial bitstream.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

configuration.

Pin Descriptions

The ADSP-2183 is available in a 128-lead LQFP package, and

Mini-BGA.

Pin

Name(s)

Address

Data

RESET

IRQ2

IRQL0,

IRQL1

IRQE

BR

BG

BGH

PMS

DMS

BMS

IOMS

CMS

RD

WR

MMAP

BMODE

CLKIN,

XTAL

PIN FUNCTION DESCRIPTIONS

#

of Input/

Pins Output Function

14 O

Address Output Pins for Program,

Data, Byte, & I/O Spaces

24 I/O

Data I/O Pins for Program and

Data Memory Spaces (8 MSBs

Are Also Used as Byte Space

Addresses)

1

I

Processor Reset Input

1

I

Edge- or Level-Sensitive

Interrupt Request

2

I

1

I

1

I

1

O

1

O

1

O

1

O

1

O

1

O

1

O

1

O

1

O

1

I

1

I

Level-Sensitive Interrupt

Requests

Edge-Sensitive Interrupt

Request

Bus Request Input

Bus Grant Output

Bus Grant Hung Output

Program Memory Select Output

Data Memory Select Output

Byte Memory Select Output

I/O Space Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

Memory Map Select Input

Boot Option Control Input

2

I

Clock or Quartz Crystal Input

Pin

Name(s)

#

of

Pins

Input/

Output Function

CLKOUT 1

O

SPORT0 5

I/O

SPORT1 5

I/O

IRD, IWR 2

I

IS

1

I

IAL

1

I

IAD

IACK

16 I/O

1

O

PWD

1

I

PWDACK 1

O

FL0, FL1,

FL2

3

O

PF7:0

8

I/O

EE

1

*

EBR

1

*

EBG

1

*

ERESET 1

*

EMS

1

*

EINT

1

*

ECLK 1

*

ELIN

1

*

ELOUT 1

*

GND

11

VDD

6

GND

22

VDD

11

Processor Clock Output.

Serial Port I/O Pins

Serial Port 1 or Two External

IRQs, Flag In and Flag Out

IDMA Port Read/Write Inputs

IDMA Port Select

IDMA Port Address Latch

Enable

IDMA Port Address/Data Bus

IDMA Port Access Ready

Acknowledge

Power-Down Control

Power-Down Control

Output Flags

Programmable I/O Pins

(Emulator Only*)

(Emulator Only*)

(Emulator Only*)

(Emulator Only*)

(Emulator Only*)

(Emulator Only*)

(Emulator Only*)

(Emulator Only*)

(Emulator Only*)

Ground Pins (LQFP)

Power Supply Pins (LQFP)

Ground Pins (Mini-BGA)

Power Supply Pins (Mini-BGA)

*These ADSP-2183 pins must be connected only to the EZ-ICE connector in

the target system. These pins have no function except during emulation, and

do not require pull-up or pull-down resistors.

Interrupts

The interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

The ADSP-2183 provides four dedicated external interrupt

input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,

SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and

FLAG_OUT, for a total of six external interrupts. The ADSP-

2183 also supports internal interrupts from the timer, the byte

DMA port, the two serial ports, software and the power-down

control circuit. The interrupt levels are internally prioritized and

individually maskable (except power-down and reset). The

IRQ2, IRQ0 and IRQ1 input pins can be programmed to be

either level- or edge-sensitive. IRQL0 and IRQL1 are level-

sensitive and IRQE is edge sensitive. The priorities and vector

addresses of all interrupts are shown in Table I.

–4–

REV. C

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