ADSP-2183KCA-210 データシートの表示（PDF） - Analog Devices
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ADSP-2183KCA-210 Datasheet PDF : 31 Pages
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ADSP-2183
In addition to the address and data bus for external memory
connection, the ADSP-2183 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2183 to continue running from on-chip memory. Normal
execution mode requires the processor to halt while buses are
granted.
The ADSP-2183 can respond to thirteen possible interrupts,
eleven of which are accessible at any given time. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal.
The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2183 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2183 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2183
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, for further details.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals, internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
21xx CORE
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
PMA BUS
DMA BUS
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
14
14
INIPNUPUTTRREGGSS
AALLUU
OUOTUPTPUUTT RREEGGSS
PMD BUS
DMD BUS
INPINUPUTTRREEGGSS
MMAACC
OUOTUPTUPUTTRREEGGSS
16
R BUS
24
BUS
EXCHANGE
16
INPUT REGS
SHIFTER
OUTPUT REGS
PROGRAM
SRAM
16k؋24
ADSP-2183 INTEGRATION
DATA
SRAM
16k؋16
BYTE
DMA
CONTROLLER
POWER
2
DOWN
CONTROL
LOGIC
8
PROGRAMMABLE
I/O
3
FLAGS
PMA BUS
DMA BUS
14
MUX
EXTERNAL
ADDRESS
BUS
PMD BUS
DMD
BUS
EXTERNAL
DATA
BUS
MUX
24
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
TIMER
5
5
INTERNAL 16
DMA
PORT
4
INTERRUPTS
Figure 1. Block Diagram
REV. C
–3–
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