ADSP-TS101S(RevA) データシートの表示（PDF） - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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ADSP-TS101S
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
Type
Term Description
MSSD1
RAS1
CAS1
LDQM1
HDQM1
SDA101
SDCKE1, 3
SDWE1
I/O/T
nc
(pu2)
I/O/T
nc
(pu2)
I/O/T
nc
(pu2)
O/T (pu2) nc
O/T (pu2) nc
O/T (pu2) nc
I/O/T
nc
(pu/pd2)
I/O/T
nc
(pu2)
Memory Select SDRAM. MSSD is asserted whenever the DSP accesses
SDRAM memory space. MSSD is a decoded memory address pin that is
asserted whenever the DSP issues an SDRAM command cycle (access to
ADDR31:26 = 0b000001). MSSD in a multiprocessor system is driven by the
master DSP.
Row Address Select. When sampled low, RAS indicates that a row address is
valid in a read or write of SDRAM. In other SDRAM accesses, RAS defines
the type of operation to execute according to SDRAM specification.
Column Address Select. When sampled low, CAS indicates that a column
address is valid in a read or write of SDRAM. In other SDRAM accesses, CAS
defines the type of operation to execute according to the SDRAM
specification.
Low Word SDRAM Data Mask. When LDQM sampled high, the DSP three-
states the SDRAM DQ buffers. LDQM is valid on SDRAM transactions when
CAS is asserted and is inactive on read transactions. On write transactions,
LDQM is active when accessing an odd address word on a 64-bit memory bus
to disable the write of the low word.
High Word SDRAM Data Mask. When HDQM sampled high, the DSP three-
states the SDRAM DQ buffers. HDQM is valid on SDRAM transactions when
CAS is asserted and is inactive on read transactions. On write transactions,
HDQM is active when accessing an even address in word accesses or is active
when memory is configured for a 32-bit bus to disable the write of the high
word.
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh
operation while the DSP executes non-SDRAM transactions.
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh
or suspend modes. A slave DSP in a multiprocessor system does not have the
pull-up or pull-down. A master DSP (or ID=0 in a single processor system)
has a 100 kΩ pull-up before granting the bus to the host, except when the
SDRAM is put in self-refresh mode. In self-refresh mode, the master has a
100 kΩ pull-down before granting the bus to the host.
SDRAM Write Enable. When sampled low while CAS is active, SDWE
indicates an SDRAM write access. When sampled high while CAS is active,
SDWE indicates an SDRAM read access. In other SDRAM accesses, SDWE
defines the type of operation to execute according to SDRAM specification.
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 kΩ to VSS; epu = External pull-up approximately 10 kΩ to VDD-IO
nc = Not connected; au = Always used.
1 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2 See ELECTRICAL CHARACTERISTICS on Page 19 for maximum and minimum current consumption for pull-up and pull-down resistances.
3 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Table 9. Pin Definitions—JTAG Port
Signal
Type
Term Description
EMU
TCK
TDI2
O (o/d)
I
I (pu3)
nc1 Emulation. Connected only to the DSP’s JTAG emulator target board
connector.
epd or Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
epu1
nc1 Test Data Input (JTAG). A serial data input of the scan path.
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 kΩ to VSS; epu = External pull-up approximately 10 kΩ to VDD-IO
nc = Not connected; au = Always used.
REV. A
–15–
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