ADBF539WBBCZ5 データシートの表示（PDF） - Analog Devices
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ADBF539WBBCZ5 Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
an external clock input to the PF1 pin (TACLK), an external
clock input to the PPI_CLK pin (TMRCLK), or to the internal
SCLK.
The timer units can be used in conjunction with UART0 to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
SERIAL PORTS (SPORTS)
The ADSP-BF539/ADSP-BF539F processors incorporate four
dual-channel synchronous serial ports for serial and multipro-
cessor communications. The SPORTs support the following
features:
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of inde-
pendent transmit and receive pins, enabling 16 channels of
I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most significant
bit first or least significant bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability – Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The processors incorporate three SPI-compatible ports that
enable the processor to communicate with multiple SPI com-
patible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSIx, and master input-slave
output, MISOx) and a clock pin (serial clock, SCKx). An SPI
chip select input pin (SPIxSS) lets other SPI devices select the
processor. For SPI0, seven SPI chip select output pins (SPI0-
SEL7–1) let the processor select other SPI devices. SPI1 and
SPI2 each have a single SPI chip select output pin (SPI1SEL1
and SPI2SEL1) for SPI point-to-point communication. Each of
the SPI select pins is a reconfigured GPIO pin. Using these pins,
the SPI ports provide a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
The SPI ports’ baud rate and clock phase/polarities are pro-
grammable, and they each have an integrated DMA controller,
configurable to support transmit or receive data streams. Each
SPI DMA controller can only service unidirectional accesses at
any given time.
The SPI port clock rate is calculated as:
SPI Clock Rate = 2---------S---P-f--IS--xC--_-L--KB---A----U----D---
where the 16-bit SPIx_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
2-WIRE INTERFACE
The processors incorporate two 2-wire interface (TWI) modules
that are compatible with the Philips Inter-IC bus standard. The
TWI modules offer the capabilities of simultaneous master and
slave operation, support for 7-bit addressing, and multimedia
data arbitration. The TWI also includes master clock synchroni-
zation and support for clock low extension.
The TWI interface uses two pins for transferring clock (SCLx)
and data (SDAx) and supports the protocol at speeds up to
400 kbps.
The TWI interface pins are compatible with 5 V logic levels.
UART PORTS
The processors incorporate three full-duplex universal asyn-
chronous receiver/transmitter (UART) ports, which are fully
compatible with PC standard UARTs. The UART ports provide
a simplified UART interface to other peripherals or hosts, sup-
porting full-duplex, DMA supported, asynchronous transfers of
serial data. The UART ports include support for 5 data bits to
8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd par-
ity. The UART ports support two modes of operation:
Rev. F | Page 10 of 60 | October 2013
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