P4C1981-25JC データシートの表示（PDF） - Semiconductor Corporation
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P4C1981-25JC Datasheet PDF : 13 Pages
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P4C1981/1981L, P4C1982/1982L
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. Parameter
-10
-12
Min Max Min Max
tRC Read Cycle Time 10
12
tAA Address Access
10
12
Time
tAC Chip Enable
Access Time
10
12
tOH Output Hold from 2
2
Address Change
tLZ Chip Enable to
2
2
Output in Low Z
tHZ Chip Disable to
6
7
Output in High Z
tOE Output Enable
6
7
Low to Data Valid
tOLZ Output Enable to 2
2
Output in Low Z
tOHZ Output Disable to
6
7
Output in High Z
tPU Chip Enable to
0
0
Power Up Time
tPD Chip Disable to
10
12
Power Down Time
-15
Min Max
15
15
15
2
2
8
8
2
9
0
15
-20
-25
Min Max Min Max
20
25
20
25
20
25
2
2
2
2
10
10
12
15
2
2
9
10
0
0
20
25
-35
Min Max
35
35
35
2
2
15
21
2
14
0
25
-45
Unit
Min Max
45
ns
45 ns
45 ns
2
ns
2
ns
15 ns
27 ns
2
ns
15 ns
0
ns
30 ns
READ CYCLE NO.1 (OE controlled)(5)
Notes:
5. WE is HIGH for READ cycle.
6. CE1, CE2 and OE are LOW for READ Cycle.
7. OE is LOW for the cycle.
8. ADDRESS must be valid prior to or coincident with, CE1, and
CE2 transition LOW.
Document # SRAM114 REV B
9. Transition is measured ±200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
10. Read Cycle Time is measured from the last valid address to
the first transitioning address.
Page 4 of 13
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