CYIL2SM1300AA(2009) データシートの表示（PDF） - Cypress Semiconductor
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CYIL2SM1300AA Datasheet PDF : 41 Pages
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CYIL2SM1300AA
Table 14. Internal Registers (continued)
Block
Register Name
tint_black_timer
rot_timer
fot_timer
fot_timer
prechpix_timer
prechpix_timer
prechcol_timer
Address [6..0]
85
86
87
88
89
90
91
rowselect_timer 92
sample_timer 93
sample_timer 94
vmem_timer
95
vmem_timer
96
delayed_rdt_timer 97
delayed_rdt_timer 98
Fix29
99
Fix30
100
Fix31
101
Fix32
102
Fix33
103
Fix34
104
Field
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
[0]
[0]
[0]
[0]
[0]
[0]
Reset Value
Description
0x06
Reserved, fixed value
0x0D
Length of ROT (granularity clock cycles)
0x36
Length of FOT (granularity clock cycles)
0x01
Length of FOT (granularity clock cycles)
0x7C
Length of pixel precharge (granularity clock cycles)
0x00
Length of pixel precharge (granularity clock cycles)
0x03
Length of column precharge (granularity clock
cycles)
0x09
Length of rowselect (granularity clock cycles)
0xF8
Length of pixel_sample (granularity clock cycles)
0x00
Length of pixel_sample (granularity clock cycles)
0x10
Length of pixel_vmem (granularity clock cycles)
0x01
Length of pixel_vmem (granularity clock cycles)
0
Readout delay for testing purposes (granularity
selectable)
0
Readout delay for testing purposes (granularity
selectable
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value
0
Reserved, fixed value, write 0x4 to it
Detailed Description of Internal Registers
The registers must be changed only during idle mode, that is,
when seqmode1[0] is ‘0’. Uploaded registers have an immediate
effect on how the frame is read out. Parameters uploaded during
readout may have an undesired effect on the data coming out of
the images.
MBS Block
The register block contains registers for sensor testing and
debugging. All registers in this block must remain unchanged
after startup.
LVDS Clock Divider Block
This block controls division of the input clock for the LVDS
transmitters or receivers. This block also enables shutting down
one or all LVDS channels. For normal operation, this register
block must remain untouched after startup.
AFE Block
This register block contains registers to shut down ADC
channels or the complete AFE block. This block also contains the
register for setting the PGA gain: AFE_mode[5:3]. Refer to
Electrical Specifications on page 5 for more details on the PGA
settings.
Biasing Block
This block contains several registers for setting biasing currents
for the sensor. Default values after startup must remain
unchanged for normal operation of the sensor.
Image Core Block
The registers in this block have an impact on the pixel array itself.
Default settings after startup must remain unchanged for normal
operation of the image sensor.
Data Block
The data block is positioned in between the analog front end
(output stage + ADCs) and the LVDS interface. It muxes the
outputs of 2 ADCs to one LVDS block and performs some minor
data handling:
■ CRC calculation and insertion
■ Training and test pattern generation
The most important registers in this block are:
Dataconfig. The dataconfig1[7:6] and dataconfig2[7:0] registers
insert a training pattern in the LVDS channels to sync the LVDS
receivers.
Document Number: 001-24599 Rev. *B
Page 15 of 41
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