UPD78064YGF-XXX-3BA(1992) データシートの表示（PDF） - NEC => Renesas Technology

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UPD78064YGF-XXX-3BA
(Rev.:1992)

8-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

mPD78062Y,78063Y,78064Y

Table 6-1 Interrupt Source List

Interrupt

Type

Non-

maskable

Maskable

Software

Default

Priority *1

Name

——

INTWDT

0

INTWDT

1

INTP0

2

INTP1

3

INTP2

4

INTP3

5

INTP4

6

INTP5

7

INTCSI0

8

INTSER

INTSR

9

INTCSI2

10

INTST

11

INTTM3

12

INTTM00

13

INTTM01

14

INTTM1

15

INTTM2

16

INTAD

——

BRK

Interrupt Source

Trigger

Watchdog timer overflow (in case of non-

maskable interrupt selection)

Watchdog timer overflow (in case of interval

timer selection)

Internal/

External

Internal

Pin input edge detection

External

Serial interface channel 0 transfer termination

Serial interface channel 2 UART reception

error generation

Serial interface channel 2 UART reception

termination

Serial interface channel 2 3-wire transfer

termination

Serial interface channel 2 UART transmission

termination

Reference time interval signal from watch

timer

16-bit timer register and capture/compare

register (CR00) match signal generation

16-bit timer register and capture/compare

register (CR01) match signal generation

8-bit timer/event counter 1 match signal

generation

8-bit timer/event counter 2 match signal

generation

A/D converter conversion termination

BRK instruction execution

Internal

Internal

Vector

Table

Address

Basic Con-

figuration

Type *2

A

0004H

B

0006H

C

0008H

000AH

000CH

D

000EH

0010H

0014H

0018H

001AH

001CH

001EH

B

0020H

0022H

0024H

0026H

0028H

003EH

E

* 1. Default priority is a priority order when more than one maskable interrupt is generated simultaneously. 0 is

the highest and 16 the lowest.

2. Basic configuration types A to E correspond to those shown on the next page.

27

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