PE9721 データシートの表示（PDF） - Peregrine Semiconductor Corp.

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PE9721

2.7 GHz Integer-N PLL with Field-Programmable EEPROM

Peregrine Semiconductor Corp. 

Functional Description

The PE9721 consists of a dual modulus prescaler,

three programmable counters, a phase detector with

charge pump, and control logic with EEPROM

memory (see Figure 1).

The dual modulus prescaler divides the VCO

frequency by either 10 or 11, depending on the state

of the internal modulus select logic. The R and M

counters divide the reference and prescaler outputs

by integer values stored in one of three selectable

registers. The modulus select logic uses the 4-bit A

counter.

The phase-frequency detector generates up and

down frequency control signals that direct the charge

pump operation, and are also used to enable a lock

detect circuit.

Frequency control data is loaded into the device via

the Serial Data Port, and can be placed in three

separate frequency registers. One of these registers

(EE register) is used to load from and write to the

non-volatile 20-bit EEPROM.

Various operational and test modes are available

through the enhancement register, which is only

accessible through the Serial Data Port (it cannot be

loaded from the EEPROM).

Main Counter Chain

The main counter chain divides the RF input

frequency, Fin, by an integer derived from the user-

defined values in the M and A counters. It operates

in two modes:

High Frequency Mode

Setting PB (prescaler bypass) LOW enables the

÷10/11 prescaler, providing operation to 2.7 GHz. In

this mode, the output from the main counter chain, fp,

is related to the VCO frequency, Fin, by the following

equation:

fp = Fin / [10 x (M + 1) + A]

(1)

where 0 ≤ A ≤ 15 and A ≤ M + 1; 1 ≤ M ≤ 511

When the loop is locked, Fin is related to the

reference frequency, fr, by the following equation:

Fin = [10 x (M + 1) + A] x (fr / (R+1))

(2)

where 0 ≤ A ≤ 15 and A ≤ M + 1; 1 ≤ M ≤ 511

A consequence of the upper limit on A is that Fin must

be greater than or equal to 90 x (fr / (R+1)) to obtain

contiguous channels. Programming the M counter

with the minimum value of 1 will result in a minimum

M counter divide ratio of 2.

Copyright  Peregrine Semiconductor Corp. 2003

Page 6 of 13

PE9721

Preliminary Specification

Programming the M and A counters with their

maximum values provides a divide ratio of 5135.

Prescaler Bypass Mode

Setting the PB bit of a frequency register HIGH

allows Fin to bypass the ÷10/11 prescaler. In this

mode, the prescaler and A counter are powered

down, and the input VCO frequency is divided by

the M counter directly. The following equation

relates Fin to the reference frequency fr:

Fin = (M + 1) x (fr / (R+1))

(3)

where 1 ≤ M ≤ 511

Reference Counter

The reference counter chain divides the reference

frequency, fr, down to the phase detector

comparison frequency, fc.

The output frequency of the 6-bit R Counter is

related to the reference frequency by the following

equation:

fc = fr / (R + 1)

(4)

where 0 ≤ R ≤ 63

Note that programming R with 0 will pass the

reference frequency, fr, directly to the phase

detector.

Phase Detector and Charge Pump

The phase detector is triggered by rising edges

from the main counter (fp) and the reference counter

(fc). It has two outputs, PD_U, and PD_D. If the

divided VCO leads the divided reference in phase

or frequency (fp leads fc), PD_D pulses LOW. If the

divided reference leads the divided VCO in phase

or frequency (fc leads fp), PD_U pulses LOW. The

width of either pulse is directly proportional to the

phase offset between the fp and fc signals.

The signals from the phase detector are also routed

to an internal charge pump. PD_U controls a

current source at pin CP, and PD_D controls a

current sink at pin CP. When using a positive Kv

VCO, PD_U pulses (current source) will increase

the VCO frequency, and PD_D pulses (current sink)

will decrease VCO frequency.

File No. 70/0098~01B | UTSi  CMOS RFIC SOLUTIONS

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