PE9721 データシートの表示（PDF） - Peregrine Semiconductor Corp.
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PE9721 Datasheet PDF : 13 Pages
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EEPROM Programming
Frequency control data that is present in the EE
Register can be written to the non-volatile EEPROM.
All 20 bits are written simultaneously in a parallel
operation. The EEPROM is guaranteed for at least
100 erase/write cycles.
Erase Cycle
The EEPROM should be taken through an erase
cycle before writing data, since the write operation
performs a logical AND of the EEPROM’s current
contents with the data in the EE Register. Erasing
the EEPROM is accomplished by holding the S_WR,
EESel, and EELoad inputs HIGH, then applying one
ERASE programming voltage pulse to the VPP input
(see Table 13). The voltage source for this operation
must be capable of supplying the EEPROM erase
cycle current (IPP_ERASE, Table 5). The timing
diagram is shown in Figure 4.
Table 13. EEPROM Programming
S_WR
1
1
EESel
1
0
EELoad
1
1
VPP
25ms @ −8.5V
25ms @ +12.5V
Function
Erase cycle
Write cycle
Figure 4. EEPROM Erase Timing Diagram
PE9721
Preliminary Specification
Write Cycle
Using the Serial Data Port, the EE Register is first
loaded with the desired data. The EEPROM is then
programmed with this data by taking the S_WR
input HIGH and EESel input LOW, then applying
one WRITE programming voltage pulse to the VPP
input. The voltage source for this operation must be
capable of supplying the EEPROM write cycle
current (IPP_WRITE, Table 5). The timing diagram
of this operation is shown in Figure 5. Programming
is completed by taking the EELoad input LOW.
Note that it is possible to erroneously overwrite the
EE Register with the EEPROM contents before the
write cycle begins by unneeded manipulation of the
EELoad bit (see Table 10).
EELoad
S_WR
EESel
tEESU
tEESU
0V
VPP_ERASE
-8.5V
tEEPW
Figure 5. EEPROM Write Timing Diagram
EESel 0V
EELoad 3V
S_WR
tEESU
tEESU
12.5V
VPP_WRITE
0V
tEEPW
Copyright Peregrine Semiconductor Corp. 2003
Page 10 of 13
File No. 70/0098~01B | UTSi CMOS RFIC SOLUTIONS
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