6700PXH データシートの表示（PDF） - Intel
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6700PXH Datasheet PDF : 194 Pages
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3.6.1.14 Offset 14Ch: PX_DERRLOG – PCI-X Uncorrectable
Data Error Log Register (D0:F0, F2) .................................................. 123
3.6.1.15 Offset 154h: PX_MISCERRLOG – Other PCI-X
Error Logs and Control Register (D0:F0, F2) ..................................... 123
3.6.1.16 Offset 170h: PXH_STPSTS – Intel® 6700PXH
64-bit PCI Hub Strap Status Register (D0:F0, F2) ............................. 125
3.6.2 Power Management Registers ......................................................................... 125
3.6.2.1 Offset 300h: PWR_ENH_BUDCAP – Power
Budgeting Capability Header Register (D0:F0, F2) ............................ 126
3.6.2.2 Offset 304h: PWR_DATSEL – Power Budgeting Data
Select Register (D0:F0, F2)................................................................ 126
3.6.2.3 Offset 308h: PWR_DATREG – Power Budgeting
Data Register (D0:F0, F2) .................................................................. 127
3.6.2.4 Offset 30Ch: PWR_BUDREG – Power Budgeting
Capability Register (D0:F0, F2) .......................................................... 127
3.6.2.5 Offset 314h: PWR_BUDREG0 – Power Budgeting
Register 0 (D0:F0, F2)........................................................................ 128
3.6.2.6 Offset 318h, 320h,...374hh: PWR_BUDREG1 —
PWR_BUDREG23 Register (D0:F0, F2) ............................................ 128
3.7
Hot Plug Controller Registers.......................................................................................... 129
3.7.1 Configuration Registers .................................................................................... 129
3.7.1.1 Offset 00h: SHPC_BASEOFF—SHPC Base Offset Register ............ 130
3.7.1.2 Offset 0Ch: SLOT_CONFIG—Slot Configuration Register ................ 130
3.7.1.3 Offset 10h: SBUS_CONFIG ............................................................... 131
3.7.1.4 Offset 12h: SHPC_MSI_CNTL—SHPC
MSI Control Register .......................................................................... 131
3.7.1.5 Offset 13h: SHPC_PROG_IF—SHPC
Programming Interface Register ........................................................ 131
3.7.1.6 Offset 14h: CONT_COMMAND—Controller
Command Register ............................................................................ 132
3.7.1.7 Offset 16h: CONT_COMMAND_STS—Controller
Command Status Register ................................................................. 132
3.7.1.8 Offset 18h: INT_LOC—Interrupt Locator Register ............................. 133
3.7.1.9 Offset 1Ch: SERR_LOC—SERR Locator Register ............................ 133
3.7.1.10 Offset 20h: SERR_INT—Controller SERR_INT
Enable Register .................................................................................. 134
3.7.2 Offset 24h – 40h: Logical Slot Registers (LSR) 1 to 6 ...................................... 134
3.7.2.1 SSTS – Slot Status Field, Bits [15:0].................................................. 135
3.7.2.2 SEVL – Slot Event Latch Field, Bits [23:16] ....................................... 136
3.7.2.3 SSIM – Slot SERR-INT Mask Field, Bits [31:24] ................................ 136
3.8
I/OxAPIC Interrupt Controller Registers (Function 1 and 3) ............................................ 137
3.8.1 PCI Configuration Space Registers .................................................................. 137
3.8.1.1 Register Summary.............................................................................. 137
3.8.1.2 Offset 00h: VID—Vendor ID Register (D0: F1, F3) ............................ 138
3.8.1.3 Offset 02h: DID—Device ID Register (D0: F1, F3)............................. 139
3.8.1.4 Offset 04h: CMD—Command Register (D0: F1, F3).......................... 139
3.8.1.5 Offset 06h: STS—Status Register (D0: F1, F3) ................................. 140
3.8.1.6 Offset 08h: REVID—Revision ID Register (D0: F1, F3) ..................... 141
3.8.1.7 Offset 09h: CC—Class Code Register (D0: F1, F3)........................... 141
3.8.1.8 Offset 0Ch: CLS—Cache Line Size Register (D0: F1, F3)................. 141
3.8.1.9 Offset 0Dh: MLAT—Master Latency Timer Register
(D0: F1, F3) ........................................................................................ 142
3.8.1.10 Offset 0Eh: HDRTYPE—Header Type Register (D0: F1, F3) ............ 142
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302628-002
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