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6700PXH データシートの表示（PDF） - Intel

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6700PXH

Intel® 6700PXH 64-bit PCI Hub

Intel

6700PXH Datasheet PDF : 194 Pages

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3.5.1.19 Offset 22h: ML—Memory Limit Register (D0:F0, F2) ........................... 93

3.5.1.20 Offset 24h: PMB—Prefetchable Memory Base Register

(D0:F0, F2) ........................................................................................... 93

3.5.1.21 Offset 26h: PML—Prefetchable Memory Limit Register

(D0:F0, F2) ........................................................................................... 94

3.5.1.22 Offset 28h: PMB_UPPER—Prefetchable Base Upper

32 Bits Register (D0:F0, F2)................................................................. 94

3.5.1.23 Offset 2Ch: PML_UPPER—Prefetchable Limit Upper

32 Bits Register (D0:F0, F2)................................................................. 95

3.5.1.24 Offset 30h: IOLU16—I/O Limit Upper 16 Bits Register

(D0:F0, F2) ........................................................................................... 95

3.5.1.25 Offset 32h: IOBU16—I/O Base Upper 16 Bits Register

(D0:F0, F2) ........................................................................................... 95

3.5.1.26 Offset 34h: CAPP—Capabilities Pointer Register

(D0:F0, F2) ........................................................................................... 95

3.5.1.27 Offset 3Ch: INTRL—Interrupt Line Register (D0:F0, F2) ..................... 96

3.5.1.28 Offset 3Dh: INTRP—Interrupt Pin Register (D0:F0, F2) ...................... 96

3.5.1.29 Offset 3Eh: BRIDGE_CNT—Bridge Control Register

(D0:F0, F2) ........................................................................................... 96

3.5.1.30 Offset 40h: CNF—Intel® 6700PXH 64-bit PCI Hub

Configuration Register (D0:F0, F2) ...................................................... 99

3.5.1.31 Offset 42h: MTT—Multi-Transaction Timer Register (D0:F0, F2) ...... 100

3.5.1.32 Offset 43h: PCLKC—PCI Clock Control Register (D0:F0, F2) ........... 100

3.5.1.33 Offset 44h: EXP_CAPID—PCI Express* Capability

Identifier Register (D0:F0, F2) ............................................................ 101

3.5.1.34 Offset 45h: EXP_NXTP—PCI Express* Next Pointer Register

(D0:F0, F2) ......................................................................................... 101

3.5.1.35 Offset 46h: EXP_CAP—PCI Express* Capability Register

(D0:F0, F2) ......................................................................................... 101

3.5.1.36 Offset 48h: EXP_DEVCAP—PCI Express* Device Capabilities

3.5.1.37 Offset 4Ch: EXP_DEVCNTL—PCI Express* Device Control

3.5.1.38 Offset 4Eh: EXP_DSTS—PCI Express* Device Status Register

(D0:F0, F2) ......................................................................................... 103

3.5.1.39 Offset 50h: EXP_LCAP—PCI Express* Link Capabilities Register

(D0:F0, F2) ......................................................................................... 104

3.5.1.40 Offset 54h: EXP_LCNTL – PCI Express* Link Control Register

(D0:F0, F2) ......................................................................................... 104

3.5.1.41 Offset 56h: EXP_LSTS – PCI Express* Link Status Register

(D0:F0, F2) ......................................................................................... 105

3.5.1.42 Offset 5Ch: MSI_CAPID— PCI Express* MSI Capability Identifier

3.5.1.43 Offset 5Dh: MSI_NXTPTR—PCI Express* MSI Next Pointer

3.5.1.44 Offset 5Eh: MSI_MCNTL—PCI Express* MSI Message Control

3.5.1.45 Offset 60h: MSI_MA—PCI Express* MSI Message Address

3.5.1.46 Offset 64h: MSI_MUA—PCI Express* MSI Message Upper

Address Register (D0:F0, F2) ............................................................ 107

3.5.1.47 Offset 68h: MSI_MD—PCI Express* MSI Message Data

302628-002

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