CY7C1443AV33(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7C1443AV33
(Rev.:2011)
(Rev.:2011)
Cypress Semiconductor
CY7C1443AV33 Datasheet PDF : 34 Pages
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CY7C1441AV33
CY7C1443AV33, CY7C1447AV33
Pin Definitions
Name
A0, A1, A
IO
Input-
Synchronous
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
GW
CLK
CE1
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
CE2
Input-
Synchronous
CE3
Input-
Synchronous
OE
Input-
Asynchronous
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
ADSC
Input-
Synchronous
BWE
ZZ
DQs
Input-
Synchronous
Input-
Asynchronous
IO-
Synchronous
DQPX
MODE
IO-
Synchronous
Input-Static
Description
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is assumed active throughout this document for
BGA. CE3 is sampled only when a new external address is loaded.
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When
LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or
left floating. ZZ pin has an internal pull down.
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write
sequences, DQPx is controlled by BW[A:H] correspondingly.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull up.
Document Number: 38-05357 Rev. *I
Page 8 of 34
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