CY7C1443AV33(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7C1443AV33
(Rev.:2011)
(Rev.:2011)
Cypress Semiconductor
CY7C1443AV33 Datasheet PDF : 34 Pages
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CY7C1441AV33
CY7C1443AV33, CY7C1447AV33
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2tCYC
–
0
Max
100
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Truth Table
tThe truth table for CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 follows.[2, 3, 4, 5, 6]
Cycle Description
Address
Used
CE1 CE2 CE3
ZZ
ADSP ADSC
ADV
WRITE OE
Deselected Cycle, Power down None
HXX L
X
L
X
X
X
Deselected Cycle, Power down None
LLXL
L
X
X
X
X
Deselected Cycle, Power down None
L XH L
L
X
X
X
X
Deselected Cycle, Power down None
LLXL
H
L
X
X
X
Deselected Cycle, Power down None
XXXL
H
L
X
X
X
Sleep Mode, Power down
None
XXXH
X
X
X
X
X
Read Cycle, Begin Burst
External L H L L
L
X
X
X
L
Read Cycle, Begin Burst
External L H L L
L
X
X
X
H
Write Cycle, Begin Burst
External L H L L
H
L
X
L
X
Read Cycle, Begin Burst
External L H L L
H
L
X
H
L
Read Cycle, Begin Burst
External L H L L
H
L
X
H
H
Read Cycle, Continue Burst
Next
XXXL
H
H
L
H
L
Read Cycle, Continue Burst
Next
XXXL
H
H
L
H
H
Read Cycle, Continue Burst
Next
HXX L
X
H
L
H
L
Read Cycle, Continue Burst
Next
HXX L
X
H
L
H
H
Write Cycle, Continue Burst
Next
XXXL
H
H
L
L
X
Write Cycle, Continue Burst
Next
HXX L
X
H
L
L
X
Read Cycle, Suspend Burst
Current X X X L
H
H
H
H
L
Read Cycle, Suspend Burst
Current X X X L
H
H
H
H
H
Read Cycle, Suspend Burst
Current H X X L
X
H
H
H
L
Read Cycle, Suspend Burst
Current H X X L
X
H
H
H
H
Write Cycle, Suspend Burst
Current X X X L
H
H
H
L
X
Write Cycle, Suspend Burst
Current H X X L
X
H
H
L
X
CLK DQ
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
L–H Tri-State
X Tri-State
L–H
Q
L–H Tri-State
L–H
D
L–H
Q
L–H Tri-State
L–H
Q
L–H Tri-State
L–H
Q
L–H Tri-State
L–H
D
L–H
D
L–H
Q
L–H Tri-State
L–H
Q
L–H Tri-State
L–H
D
L–H
D
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5.
The SRAM always initiates a read cycle when
the ADSP or with the assertion of ADSC. As a
ADSP
result,
is asserted,
OE must be
rdergivaerndlHesIGs HofpthrieorsttoatteheofsGtaWrt ,oBf tWheEw, orirteBcWycXl.eWtoritaellsomw athyeoocucutpruotsnltyootrni-ssutabtsee. qOuEenist
clocks
a don't
after
care
for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05357 Rev. *I
Page 11 of 34
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