CY7C194BN-15PC(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7C194BN-15PC Datasheet PDF : 15 Pages
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CY7C194BN
Timing Waveforms (continued)
Address
Figure 2. Read Cycle No. 2 [10, 11, 12]
tRC
CE
OE
Data Out
VCC
Current
Address
CE
WE
Data
In/Out
tACE
tHZCE
High Z
ICC
ISB
tLZCE
tPU
tLZOE
tDOE
50%
Figure 3. Write Cycle No. 1 (WE Controlled) [10, 13]
tHZOE
Data Valid
High Z
tPD
50%
t WC
tSA
Undefined
see footnotes
tSCE
tAW
tHZWE
tHA
tPWE
tSD
Data-In Valid
tHD
tLZWE
Undefined
See Footnotes
Notes
10. Tested initially and after any design or process change that may affect these parameters
11. WE is HIGH in read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. The minimum write cycle time is the sum of tHZWE and tSD.
Document #: 001-06446 Rev. *D
Page 9 of 15
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