CY7C194BN-15PC(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7C194BN-15PC Datasheet PDF : 15 Pages
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AC Electrical Characteristics
Parameter [4, 5, 6, 7]
Description
tRC
tAA
tOHA
tACE
tLZCE
tHZCE
tPU
tPD
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Read cycle time
Address to data valid
Data hold from address change
CE to data valid
CE to Low Z
CE to High Z
CE to Power-up
CE to Power-down
Write cycle time
CE to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
Data set-up to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
Timing Waveforms
Figure 1. Read Cycle No. 1 [8, 9]
Address
Data Out
tRC
tAA
tOHA
Previous Data Valid
CY7C194BN
15 ns
Unit
Min
Max
15
–
ns
–
15
ns
3
–
ns
–
15
ns
3
–
ns
–
7
ns
0
–
ns
–
15
ns
15
–
ns
10
–
ns
10
–
ns
0
–
ns
0
–
ns
9
–
ns
8
–
ns
0
–
ns
–
7
ns
3
–
ns
Data Valid
Notes
4. Tested initially and after any design or process change that may affect these parameters
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device.
6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
7. tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage.
8. Device is continuously selected. CE = VIL.
9. WE is HIGH for Read Cycle.
Document #: 001-06446 Rev. *D
Page 8 of 15
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