ADSST-21065LKCA-240 データシートの表示（PDF） - Analog Devices

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ADSST-21065LKCA-240

High End, Multichannel, 32-Bit Floating-Point Audio Processor

Analog Devices 

SST-Melody-SHARC

Mnemonic

Type

Function

HBG

I/O

CS

I/A

Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control

of the external bus. HBG is asserted by the SST-Melody-SHARC until HBR is released. In a multi-

processor system, HBG is output by the SST-Melody-SHARC bus master.

Chip Select. Asserted by host processor to select the SST-Melody-SHARC.

REDY (O/D) O

DMAR1

DMAR2

DMAG1

DMAG2

BR2–1

ID1–0

I/A

I/A

O/T

O/T

I/O/S

I

Host Bus Acknowledge. The SST-Melody-SHARC deasserts REDY to add wait states to an asyn-

chronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by

default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY

will only be output if the CS and HBR inputs are asserted.

DMA Request 1 (DMA Channel 9)

DMA Request 2 (DMA Channel 8)

DMA Grant 1 (DMA Channel 9)

DMA Grant 2 (DMA Channel 8)

Multiprocessing Bus Requests. Used by multiprocessing SST-Melody-SHARCs to arbitrate for bus

mastership. An SST-Melody-SHARC drives its own BRx line (corresponding to the value of its ID2–0

inputs) only and monitors all others. In a uniprocessor system, tie both BRx pins to VDD.

Multiprocessing ID. Determines which multiprocessor bus request (BR1 – BR2) is used by

SST-Melody-SHARC. ID = 01 corresponds to BR1, ID = 10 corresponds to BR2. ID = 00 in single-

processor systems. These lines are a system configuration selection that should be hard-wired or

changed only at reset.

CPA (O/D)

I/O

Core Priority Access. Asserting its CPA pin allows the core processor of an SST-Melody-SHARC bus

slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open

drain output that is connected to both SST-Melody-SHARCs in the system. The CPA pin has an

internal 5 kΩ pull-up resistor. If core access priority is not required in a system, leave the CPA pin

unconnected.

DTxX

O

Data Transmit (Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50 kΩ internal pull-up resistor.

DRxX

I

Data Receive (Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 kΩ internal pull-up resistor.

TCLKx

I/O

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.

RCLKx

I/O

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

TFSx

I/O

Transmit Frame Sync (Serial Ports 0, 1)

RFSx

I/O

Receive Frame Sync (Serial Ports 0, 1)

BSEL

BMS

I

I/O/T*

EPROM Boot Select. When BSEL is high , the SST-Melody-SHARC is configured for booting from an

8-bit EPROM. When BSEL is low, the BSEL and BMS inputs determine booting mode.

See BMS for details. This signal is a system configuration selection that should be hardwired.

Boot Memory Select. Output: used as chip select for boot EPROM devices (when BSEL = 1). In a

multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting

will occur and that the SST-Melody-SHARC will begin executing instructions from external memory.

See following table. This input is a system configuration selection that should be hardwired.

BSEL

1

0

0

BMS

Output

1 (Input)

0 (Input)

Booting Mode

EPROM (connect BMS to EPROM chip select).

Host processor (HBW [SYSCON] bit selects host bus width).

No booting. Processor executes from external memory.

CLKIN

I

Clock In. Used in conjunction with XTAL, configures the SST-Melody-SHARC to use either its inter-

nal clock generators or an external clock source. The external crystal should be rated at 1× frequency.

Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. The

SST-Melody-SHARC’s internal clock generator multiplies the 1× clock to generate 2× clock for its

core and SDRAM. It drives 2× clock out on the SDCLKx pins for the SDRAM interface to use. See

also SDCLKx.

Connecting the 1× external clock to CLKIN while leaving XTAL unconnected configures the

SST-Melody-SHARC to use the external clock source. The instruction cycle rate is equal to 2×

CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency.

RESET

I/A

Processor Reset. Resets the SST-Melody-SHARC to a known state and begins execution at the pro-

gram memory location specified by the hardware reset vector address. This input must be asserted at

power-up.

*Three-statable only in EPROM boot mode (when BMS is an output).

REV. 0

–9–

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