ADSST-21065LKCA-240 データシートの表示（PDF） - Analog Devices
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ADSST-21065LKCA-240 Datasheet PDF : 20 Pages
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SST-Melody-SHARC–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS1
Parameter
VDD
TCASE
VIH
VIL1
VIL2
Test
Conditions
Supply Voltage
Case Operating Temperature
High Level Input Voltage
Low Level Input Voltage2
Low Level Input Voltage3
@ VDD = max
@ VDD = min
@ VDD = min
C Grade
Min Max
3.13 3.60
–40 +100
2.0
VDD + 0.5
–0.5 +0.8
–0.5 +0.7
K Grade
Min Max
Unit
3.13 3.60
V
0
+85
°C
2.0
VDD + 0.5 V
–0.5 +0.8
V
–0.5 +0.7
V
NOTES
1See Environmental Conditions section for information on thermal specifications.
2Applies to input and bidirectional pins: DATA31–0, ADDR23–0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, CS, DMAR1, DMAR2, BR2–1, ID2–0,
RPBA, CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST,
PWM_EVENT0, PWM_EVENT1, RAS, CAS, SDWE, SDCKE.
3Applies to input pin CLKIN.
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
C and K Grades
Min
Max
Unit
VOH
High Level Output Voltage1
@ VDD = min, IOH = –2.0 mA2
2.4
VOL
Low Level Output Voltage1
@ VDD = min, IOL = +4.0 mA2
IIH
High Level Input Current3
@ VDD = max, VIN = VDD max
IIL
Low Level Input Current3
@ VDD = max, VIN = 0 V
IILP
Low Level Input Current4
@ VDD = max, VIN = 0 V
IOZH
Three-State Leakage Current5, 6, 7, 8 @ VDD = max, VIN = VDD max
IOZL
Three-State Leakage Current5
@ VDD = max, VIN = 0 V
IOZLS
Three-State Leakage Current6
@ VDD = max, VIN = 0 V
IOZLA
Three-State Leakage Current9
@ VDD = max, VIN = 1.5 V
IOZLAR
Three-State Leakage Current8
@ VDD = max, VIN = 0 V
IOZLC
Three-State Leakage Current7
@ VDD = max, VIN = 0 V
CIN
Input Capacitance10, 11
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
V
0.4
V
10
µA
10
µA
150
µA
10
µA
8
µA
150
µA
350
µA
4
mA
1.5
mA
8
pF
NOTES
1Applies to output and bidirectional pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, HBG, REDY, DMAG1, DMAG2, BR2–1, CPA,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL, BMS, TDO, EMU, BMSTR, PWM_EVENT0,
PWM_EVENT1, RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10.
2See Output Drive Current section for typical drive current capabilities.
3Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID1–0, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2 kΩ
during reset in a multiprocessor system, when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
4Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B, TRST, TMS, TDI.
5Applies to three-statable pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS,
DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10, and EMU (note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system,
when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership).
6Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.
7Applies to CPA pin.
8Applies to ACK pin when pulled up.
9Applies to ACK pin when keeper latch enabled.
10Guaranteed but not tested.
11Applies to all signal pins.
Specifications subject to change without notice.
–2–
REV. 0
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