ADSST-21065LKCA-264 データシートの表示（PDF） - Analog Devices

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ADSST-21065LKCA-264

High End, Multichannel, 32-Bit Floating-Point Audio Processor

Analog Devices 

SST-Melody-SHARC

PIN FUNCTION DESCRIPTIONS

SST-Melody-SHARC pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with

respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDD or GND, except for ADDR23–0, DATA31–0, FLAG11–0, SW, and inputs that

have internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI), which can be left

floating. These pins have a logic-level hold circuit that prevents the input from floating internally.

Mnemonic

ADDR23–0

Type

I/O/T

DATA31–0

I/O/T

MS3–0

I/O/T

RD

I/O/T

WR

I/O/T

SW

I/O/T

ACK

I/O/S

SBTS

I/S

IRQ2–0

FLAG11–0

HBR

I/A

I/O/A

I/A

Function

External Bus Address. The SST-Melody-SHARC outputs addresses for external memory and periph-

erals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the

IOP registers of the other SST-Melody-SHARC. The SST-Melody-SHARC inputs addresses when a

host processor or multiprocessing bus master is reading or writing its IOP registers.

External Bus Data. The SST-Melody-SHARC inputs and outputs data and instructions on these pins.

The external databus transfers 32-bit, single-precision, floating-point data and 32-bit fixed-point data

over bits 31-0. 16-Bit short word data is transferred over Bits 15-0 of the bus. Pull-up resistors on

unused DATA pins are not necessary.

Memory Select Lines. These lines are asserted as chip selects for the corresponding banks of external

memory. Internal ADDR25–24 are decoded into MS3–0. The MS3–0 lines are decoded memory ad-

dress lines that change at the same time as the other address lines. When no external memory access

is occurring, the MS3–0 lines are inactive; they are active, however, when a conditional memory

access instruction is executed, whether or not the condition is true. Additionally, an MS3–0 line that is

mapped to SDRAM may be asserted even when no SDRAM access is active. In a multiprocessor system,

the MS3–0 lines are output by the bus master.

Memory Read Strobe. This pin is asserted when the SST-Melody-SHARC reads from external

memory devices or from the IOP register of another SST-Melody-SHARC. External devices (includ-

ing another SST-Melody-SHARC) must assert RD to read from the SST-Melody-SHARC’s IOP

registers. In a multiprocessor system, RD is output by the bus master and is input by another

SST-Melody-SHARC.

Memory Write Strobe. This pin is asserted when the SST-Melody-SHARC writes to external

memory devices or to the IOP register of another SST-Melody-SHARC. External devices must assert

WR to write to the SST-Melody-SHARC’s IOP registers. In a multiprocessor system, WR is output

by the bus master and is input by the other SST-Melody-SHARC.

Synchronous Write Select. This signal interfaces the SST-Melody-SHARC to synchronous memory

devices (including another SST-Melody-SHARC). The SST-Melody-SHARC asserts SW to provide

an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g.,

in a conditional write instruction). In a multiprocessor system, SW is output by the bus master and is

input by the other SST-Melody-SHARC to determine if the multiprocessor access is a read or write. SW

is asserted at the same time as the address output.

Memory Acknowledge. External devices can deassert ACK to add wait states to an external memory

access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an

external memory access. The SST-Melody-SHARC deasserts ACK as an output to add wait states to a

synchronous access of its IOP registers. In a multiprocessor system, a slave SST-Melody-SHARC deasserts

the bus master’s ACK input to add wait state(s) to an access of its IOP registers. The bus master has a

keeper latch on its ACK pin that maintains the input at the level to which it was last driven.

Suspend Bus Three-State. External devices can assert SBTS to place the external bus address, data,

selects, and strobes—but not SDRAM control pins—in a high impedance state for the following cycle.

If the SST-Melody-SHARC attempts to access external memory while SBTS is asserted, the proces-

sor will halt and the memory access will not finish until SBTS is deasserted. SBTS should only be

used to recover from host processor/SST-Melody-SHARC deadlock.

Interrupt Request Lines. May be either edge-triggered or level-sensitive.

Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can be tested

as a condition. As an output, it can be used to signal external peripherals.

Host Bus Request. Must be asserted by a host processor to request control of the SST-Melody-SHARC’s

external bus. When HBR is asserted in a multiprocessing system, the SST-Melody- SHARC that is

bus master will relinquish the bus and assert HBG. To relinquish the bus, the SST-Melody-SHARC

places the address, data, select, and strobe lines in a high impedance state. It does, however, con-

tinue to drive the SDRAM control pins. HBR has priority over all SST-Melody-SHARC bus

requests (BR2–1) in a multiprocessor system.

–8–

REV. 0

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