IMIC9530CT データシートの表示（PDF） - Silicon Laboratories
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IMIC9530CT Datasheet PDF : 10 Pages
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C9530
PCIX I/O System Clock Generator with EMI Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33.3 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• Output grouped in two banks of five clocks each
• One REF XIN clock output
• SMBus clock control interface for individual clock
disabling and SSCG control and individual back
frequency selection
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter < 250 psec (175 psec with all outputs at the
same frequency)
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pins for entire output bank enable control and
testability
• 48-pin SSOP and TSSOP packages
Block Diagram
SSCG#
SSCG
Logic
XIN
XOUT
SDATA
SCLK
IA(0:2)
SA(0,1)
SB(0,1)
I2C
Control
Logic
/N 1
0
0
/N 1
AGOOD#
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
OEA
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
OEB
BGOOD#
REF
Table 1. Test Mode Logic Table[1]
OEA
OEB
HIGH
HIGH
HIGH
HIGH
LOW
Input Pins
SA1
SB1
LOW
LOW
HIGH
HIGH
X
SA0
SB0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLKA
CLKB
REF
XIN
XIN
2 * XIN
XIN
3 * XIN
XIN
4 * XIN
XIN
Three-state Three-state
Pin Configuration
REF 1
VDD 2
XIN 3
XOUT 4
VSS 5
SA0 6
SA1 7
VSS 8
CLKA0 9
CLKA1 10
VDDA 11
CLKA2 12
VSS 13
VDDA 14
CLKA3 15
CLKA4 16
VSS 17
AGOOD# 18
VSS 19
IA0 20
IA1 21
IA2 22
AVDD 23
OEA 24
48 SDATA
47 SCLK
46 VDD
45 VSS
44 VDD
43 SB0
42 SB1
41 VSS
40 CLKB0
39 CLKB1
38 VDDB
37 CLKB2
36 VSS
35 VDDB
34 CLKB3
33 CLKB4
32 VSS
31 BGOOD#
30 AVDD
29 AVDD
28 VSS
27 SSCG#
26 VSS
25 OEB
Note:
1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state
REF.
....................... Document #: 38-07033 Rev. *C Page 1 of 10
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