MAX705C データシートの表示（PDF） - Maxim Integrated

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MAX705C

Low-Cost, μP Supervisory Circuits

Maxim Integrated 

MAX705–MAX708/MAX813L

MAX705–MAX708/MAX813L

Low-Cost, μP Supervisory Circuits

Power-Fail Comparator

The power-fail comparator can be used for various

purposes because its output and noninverting input are

not internally connected. The inverting input is internally

connected to a 1.25V reference.

tWP

tWD

tWD

+5V

WDI

0V

+5V

WDO

0V

+5V

RESET

0V

+5V

(RESET) 0V

RESET EXTERNALLY

TRIGGERED BY MR

( ) ARE FOR MAX813L ONLY.

tWD

tRS

Figure 3. MAX705/MAX706/MAX813L Watchdog Timing

VCC

+5V

RESET

0V

+5V

MR

0V

+5V

WDO

0V

VRT

VRT

tRS

tRS

tMD

tMR

MR EXTERNALLY DRIVEN LOW

To build an early-warning circuit for power failure, connect

the PFI pin to a voltage divider (see Typical Operating

Circuit). Choose the voltage divider ratio so that the

voltage at PFI falls below 1.25V just before the +5V

regulator drops out. Use PFO to interrupt the μP so it can

prepare for an orderly power-down.

Applications Information

Ensuring a Valid RESET Output Down to

VCC = 0V

When VCC falls below 1V, the MAX705–MAX708 RESET

output no longer sinks current—it becomes an open

circuit. High-impedance CMOS logic inputs can drift

to undetermined voltages if left undriven. If a pulldown

resistor is added to the RESET pin, as shown in Figure

5, any stray charge or leakage currents will be drained

to ground, holding RESET low. Resistor value (R1) is not

critical. It should be about 100kΩ, large enough not to load

RESET and small enough to pull RESET to ground.

Monitoring Voltages Other Than the

Unregulated DC Input

Monitor voltages other than the unregulated DC by

connecting a voltage-divider to PFI and adjusting the ratio

appropriately. If required, add hysteresis by connecting a

resistor (with a value approximately 10 times the sum of

the two resistors in the potential divider network) between

PFI and PFO. A capacitor between PFI and GND reduces

the power-fail circuit’s sensitivity to high-frequency noise

on the line being monitored. RESET can be asserted on

other voltages in addition to the +5V VCC line. Connect

PFO to MR to initiate a RESET pulse when PFI drops

below 1.25V. Figure 6 shows the MAX705–MAX708

configured to assert RESET when the +5V supply falls

below the reset threshold, or when the +12V supply falls

below approximately 11V.

Monitoring a Negative Voltage

The power-fail comparator can also monitor a negative

supply rail (Figure 7). When the negative rail is good (a

negative voltage of large magnitude), PFO is low, and

when the negative rail is degraded (a negative voltage of

lesser magnitude), PFO is high. By adding the resistors

and transistor as shown, a high PFO triggers a reset.

As long as PFO remains high, the MAX705–MAX708/

MAX813L keep reset asserted (RESET = low, RESET =

high). Note that this circuit’s accuracy depends on the PFI

threshold tolerance, the VCC line, and the resistors.

Figure 4. MAX705/MAX706 RESET, MR, and WDO Timing with

WDI Three Stated. The MAX707/MAX708/MAX813L RESET

output is the inverse of RESET shown.

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