MAX705C データシートの表示（PDF） - Maxim Integrated

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MAX705C

Low-Cost, μP Supervisory Circuits

Maxim Integrated 

MAX705–MAX708/MAX813L

MAX705–MAX708/MAX813L

Low-Cost, μP Supervisory Circuits

6

WDI

WATCHDOG

TRANSITION

DETECTOR

VCC

MR 1

2

VCC

250µA

WATCHDOG

TIMER

TIMEBASE FOR

RESET AND

WATCHDOG

RESET

GENERATOR

8 WDO

7 RESET

(RESET)

PFI 4

4.65V*

1.25V

MAX705

MAX706

MAX813L

5 PFO

* 4.40V FOR MAX7O6.

( ) ARE FOR MAX813L ONLY.

3 GND

Figure 1. MAX705/MAX706/MAX813L Block Diagram

Detailed Description

Reset Output

A microprocessor’s (μP’s) reset input starts the μP in a

known state. Whenever the μP is in an unknown state, it

should be held in reset. The MAX705–MAX708/MAX813L

assert reset during power-up and prevent code execution

errors during power-down or brownout conditions.

On power-up, once VCC reaches 1V, RESET is a

guaranteed logic low of 0.4V or less. As VCC rises, RESET

stays low. When VCC rises above the reset threshold, an

internal timer releases RESET after about 200ms. RESET

pulses low whenever VCC dips below the reset threshold,

i.e. brownout condition. If brownout occurs in the middle

of a previously initiated reset pulse, the pulse continues

for at least another 140ms. On power-down, once VCC

falls below the reset threshold, RESET stays low and is

guaranteed to be 0.4V or less until VCC drops below 1V.

The MAX707/MAX708/MAX813L active-high RESET

output is simply the complement of the RESET output,

and is guaranteed to be valid with VCC down to 1.1V.

Some μPs, such as Intel’s 80C51, require an active-high

reset pulse.

Watchdog Timer

The MAX705/MAX706/MAX813L watchdog circuit

monitors the μP’s activity. If the μP does not toggle the

watchdog input (WDI) within 1.6sec and WDI is not three

VCC

MR 1

250µA

2

VCC

4

PFI

4.65V*

1.25V

* 4.40V FOR MAX7O6.

RESET

GENERATOR

MAX707

MAX708

3 GND

8

RESET

7 RESET

5 PFO

Figure 2. MAX707/MAX708 Block Diagram

stated, WDO goes low. As long as RESET is asserted or

the WDI input is three stated, the watchdog timer stays

cleared and will not count. As soon as reset is released

and WDI is driven high or low, the timer starts counting.

Pulses as short as 50ns can be detected.

Typically, WDO is not connected to the nonmaskable

interrupt input (NMI) of a μP. When VCC drops below

the reset threshold, WDO goes low whether or not

the watchdog timer has timed out yet. Normally this

would trigger an NMI interrupt, but RESET goes low

simultaneously, and thus overrides the NMI interrupt.

If WDI is left unconnected, WDO can be used as a low-

line output. Since floating WDI disables the internal timer,

WDO goes low only when VCC falls below the reset

threshold, thus functioning as a low-line output.

The MAX705/MAX706 have a watchdog timer and a

RESET output. The MAX707/MAX708 have both active-

high and active-low reset outputs. The MAX813L has both

an active-high reset output and a watchdog timer.

Manual Reset

The manual-reset input (MR) allows reset to be triggered

by a pushbutton switch. The switch is effectively

debounced by the 140ms minimum reset pulse width. MR

is TTL/CMOS-logic compatible, so it can be driven by an

external logic line. MR can be used to force a watchdog

timeout to generate a reset pulse in the MAX705/ MAX706/

MAX813L. Simply connect WDO to MR.

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