ADSP-21065LKCA-264 データシートの表示（PDF） - Analog Devices

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ADSP-21065LKCA-264

DSP Microcomputer

Analog Devices 

ADSP-21065L

GENERAL DESCRIPTION

The ADSP-21065L is a powerful member of the SHARC

family of 32-bit processors optimized for cost sensitive appli-

cations. The SHARC—Super Harvard Architecture—offers the

highest levels of performance and memory integration of any

32-bit DSP in the industry—they are also the only DSP in the

industry that offer both fixed and floating-point capabilities,

without compromising precision or performance.

The ADSP-21065L is fabricated in a high speed, low power

CMOS process, 0.35 mm technology. With its on-chip instruc-

tion cache, the processor can execute every instruction in a

single cycle. Table I lists the performance benchmarks for the

ADSP-21065L.

The ADSP-21065L SHARC combines a floating-point DSP

core with integrated, on-chip system features, including a

544 Kbit SRAM memory, host processor interface, DMA con-

troller, SDRAM controller, and enhanced serial ports.

Figure 1 shows a block diagram of the ADSP-21065L, illustrat-

ing the following architectural features:

Computation Units (ALU, Multiplier, and Shifter) with a

Shared Data Register File

Data Address Generators (DAG1, DAG2)

Program Sequencer with Instruction Cache

Timers with Event Capture Modes

On-Chip, dual-ported SRAM

External Port for Interfacing to Off-Chip Memory and

Peripherals

Host Port and SDRAM Interface

DMA Controller

Enhanced Serial Ports

JTAG Test Access Port

Table I. Performance Benchmarks

Benchmark

Cycle Time

1024-Pt. Complex FFT

(Radix 4, with Digit Reverse)

Matrix Multiply (Pipelined)

[3 ¥ 3] ¥ [3 ¥ 1]

[4 ¥ 4] ¥ [4 ¥ 1]

FIR Filter (per Tap)

IIR Filter (per Biquad)

Divide Y/X

Inverse Square Root (1/÷x)

DMA Transfers

Timing

15.00 ns

Cycles

1

0.274 ns

18221

135 ns

9

240 ns

16

15 ns

1

60 ns

4

90 ns

6

135 ns

9

264 Mbytes/sec.

ADSP-21000 FAMILY CORE ARCHITECTURE

The ADSP-21065L is code and function compatible with the

ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L

includes the following architectural features of the SHARC

family core.

CLOCK

RESET

01

ADSP-21065L

#1

CLKIN

RESET

ID1-0

ADDR23-0

SPORT0 DATA31-0

TX0_A

RD

TX0_B

WR

RX0_A

RX0_B

SPORT1

TX1_A

TX1_B

ACK

MS3-0

BMS

SBTS

SW

CS

RX1_A

RX1_B

HBR

HBG

REDY

CONTROL

RAS

CAS

DQM

SDWE

SDCLK1-0

SDCKE

SDA10

CPA

BR2

BR1

CS

BOOT

ADDR EPROM

DATA (OPTIONAL)

HOST

PROCESSOR

(OPTIONAL)

CS

ADDR

DATA

ADDR

DATA

CS

SDRAM

(OPTIONAL)

RAS

CAS

DQM

WE

CLK

CKE

A10

Figure 2. ADSP-21065L Single-Processor System

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier, and shifter all

perform single-cycle instructions. The three units are arranged

in parallel, maximizing computational throughput. Single multi-

function instructions execute parallel ALU and multiplier

operations. These computation units support IEEE 32-bit

single-precision floating-point, extended precision 40-bit floating-

point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is used for transferring data

between the computation units and the data buses, and for

storing intermediate results. This 10-port, 32-register (16 primary,

16 secondary) register file, combined with the ADSP-21000

Harvard architecture, allows unconstrained data flow between

computation units and internal memory.

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-21065L features an enhanced Super Harvard Archi-

tecture in which the data memory (DM) bus transfers data and

the program memory (PM) bus transfers both instructions and

data (see Figure 1). With its separate program and data memory

buses, and on-chip instruction cache, the processor can simulta-

neously fetch two operands and an instruction (from the cache),

all in a single cycle.

Instruction Cache

The ADSP-21065L includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and two

data values. The cache is selective—only the instructions that

fetches conflict with PM bus data accesses are cached. This

allows full-speed execution of core, looped operations such as

digital filter multiply-accumulates and FFT butterfly processing.

Data Address Generators with Hardware Circular Buffers

The ADSP-21065L’s two data address generators (DAGs)

implement circular data buffers in hardware. Circular buffers

allow efficient programming of delay lines and other data

REV. C

–3–

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