HM-6551-9 データシートの表示（PDF） - Intersil

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HM-6551-9

256 x 4 CMOS RAM

Intersil 

Timing Waveforms

A

E

S2

(8) TAVEL

TEHEL

(7)

(9)

TS2LEL

HM-6551

(10)

TELAX

VALID

TELS2X

(11)

(19) TELEL

TELEH (6)

(8) TAVEL

NEXT

TELEL (7)

(9)

TS2LEL

D

TELQV (1)

TAVQV (2)

Q

VALID OUTPUT

(3) TS1LQX

TS1HQZ (5)

S1

W

HIGH

TIME

REFERENCE

TIME

REFERENCE

E

-1

H

0

1

L

2

L

3

4

H

5

-1

0

1

2

3

4

5

FIGURE 1. READ CYCLE

TRUTH TABLE

INPUTS

OUTPUTS

S1

S2

W

A

D

Q

FUNCTION

H

X

X

X

X

Z

Memory Disabled

X

L

H

V

X

Z

Addresses and S2 are Latched,

Cycle Begins

L

X

H

X

X

X

Output Enabled but Undefined

L

X

H

X

X

V

Data Output Valid

L

X

H

X

X

V

Outputs Latched, Valid Data,

S2 Unlatches

H

X

X

X

X

Z

Prepare for Next Cycle

(Same as -1)

X

L

H

V

X

Z

Cycle Ends, Next Cycle Begins

(Same as 0)

The HM-6551 Read Cycle is initiated by the falling edge of E.

This signal latches the input address word and S2 into on

chip registers, providing the minimum setup and hold times

are met. After the required hold time, these inputs may

change state without affecting device operation. S2 acts as a

high order address and simplifies decoding. For the output to

be read, E, S1 must be low and W must be high. S2 must

have been latched low on the falling edge of E. The output

data will be valid at access time (TELQV). The HM-6551 has

output data latches that are controlled by E. On the rising

edge of E the present data is latched and remains in that

state until E falls. Also on the rising edge of E, S2 unlatches

and controls the outputs along with S1. Either or both S1 or

S2 may be used to force the output buffers into a high

impedance state.

6-5

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