HM-6551-9 データシートの表示（PDF） - Intersil
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HM-6551-9 Datasheet PDF : 7 Pages
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HM-6551
AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6551B-9, HM-6551-9)
LIMITS
SYMBOL
PARAMETER
HM-6551B-9
MIN MAX
HM-6551-9
MIN MAX
UNITS
TEST
CONDITIONS
(1) TELQV
Chip Enable Access Time
-
220
-
300
ns
(Notes 1, 3)
(2) TAVQV
Address Access Time
-
220
-
300
ns
(Notes 1, 3, 4)
(3) TS1LQX Chip Select 1 Output Enable Time
5
130
5
150
ns
(Notes 2, 3)
(4) TWLQZ Write Enable Output Disable Time
-
130
-
150
ns
(Notes 2, 3)
(5) TS1HQZ Chip Select 1 Output Disable Time
-
130
-
150
ns
(Notes 2, 3)
(6) TELEH
Chip Enable Pulse Negative Width
220
-
300
-
ns
(Notes 1, 3)
(7) TEHEL
Chip Enable Pulse Positive Width
100
-
100
-
ns
(Notes 1, 3)
(8) TAVEL
Address Setup Time
0
-
0
-
ns
(Notes 1, 3)
(9) TS2LEL Chip Select 2 Output Disable Time
0
-
0
-
ns
(Notes 1, 3)
(10) TELAX
Address Hold Time
40
-
50
-
ns
(Notes 1, 3)
(11) TELS2X Chip Select 2 Hold Time
40
-
50
(Notes 1, 3)
(12) TDVWH Data Setup Time
100
-
150
-
ns
(Notes 1, 3)
(13) TWHDX Data Hold Time
0
-
0
-
ns
(Notes 1, 3)
(14) TWLS1H Chip Select 1 Write Pulse Setup Time
120
-
180
-
ns
(Notes 1, 3)
(15) TWLEH Chip Enable Write Pulse Setup Time
120
-
180
-
ns
(Notes 1, 3)
(16) TS1LWH Chip Select 1 Write Pulse Hold Time
120
-
180
-
ns
(Notes 1, 3)
(17) TELWH Chip Enable Write Pulse Hold Time
120
-
180
-
ns
(Notes 1, 3)
(18) TWLWH Write Enable Pulse Width
120
-
180
-
ns
(Notes 1, 3)
(19) TELEL
Read or Write Cycle Time
320
-
400
-
ns
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-4
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