UT54LVDS032LVT-UPA データシートの表示（PDF） - Aeroflex UTMC
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UT54LVDS032LVT-UPA Datasheet PDF : 11 Pages
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RIN1-
RIN1+
ROUT1
EN
ROUT2
RIN2+
RIN2-
V SS
1
16
2
15
3
14
UT54LVDS032LV
4
Receiver
13
5
12
6
11
7
10
8
9
VDD
RIN4-
RIN4+
ROUT4
EN
ROUT3
RIN3+
R IN3-
Figure 2. UT54LVDS032LVT Pinout
APPLICATIONS INFORMATION
The UT54LVDS032LVT receiver’s intended use is primarily in
an uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media which may be
a standard twisted pair cable, a parallel pair cable, or simply
PCB traces. Typically, the characteristic impedance of the media
is in the range of 100Ω. An integrated termination resistor of
105Ω is used to match the media . The termination resistor
converts the current sourced by the driver into voltages that are
detected by the receiver. Other configurations are possible such
as a multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance discontinuities,
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.
TRUTH TABLE
Enables
EN
EN
L
H
Input
RIN+ - RIN-
X
Output
ROUT
Z
ENABLE
1/4 UT54LVDS032LV
DATA
T INPUT
RT 100Ω
+
- DATA
OUTPUT
N 1/4 UT54LVDS031LV
EFigure 3. Point-to-Point Application
All other combinations VID > 0.1V
H
of ENABLE inputs
VID < -0.1V
L
M Full Fail-safe
H
OPEN/SHORT or
P Terminated
O PIN DESCRIPTION
L Pin No.
2, 6, 10, 14
E 1, 7, 9, 15
V 3, 5, 11, 13
E 4
Name
RIN+
RIN-
ROUT
EN
D 12
EN
IN 16
VD D
Description
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
Active high enable pin, OR-ed
with EN
Active low enable pin, OR-ed
with EN
Power supply pin, +3.3 + 0.3V
The UT54LVDS032LVTdifferential line receiver is capable of
detecting signals as low as 100mV, over a + 1V common-mode
range centered around +1.2V. This is related to the driver offset
voltage which is typically +1.2V. The driven signal is centered
around this voltage and may shift +1V around this center point.
The +1V shifting may be the result of a ground potential
difference between the driver’s ground reference and the
receiver’s ground reference, the common-mode effects of
coupled noise or a combination of the two. Both receiver input
pins should honor their specified operating input voltage range
of 0V to +2.4V (measured from each pin to ground).
The integrated termination resistor is a nominal 105Ω when V DD
is 3.0 to 3.6V. In cold spare mode, the integrated termination
resistor is 145Ω.
8
VSS
Ground pin
2
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