NCV8660C データシートの表示（PDF） - ON Semiconductor
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NCV8660C Datasheet PDF : 11 Pages
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NCV8660C
IN
OUT
Reset Delay Time
RO
t < Reset Reaction Time
t
OUT Reset Threshold plus Hysteresis
OUT Reset Threshold
t
Reset
Threshold
Plus
Hysteresis
Thermal
Shutdown
Voltage Dip
at Input
Reset Delay Time
Secondary Overload
Spike at Output
Thermal Shutdown
minus
Thermal Hysteresis
Figure 19. Reset Timing
Reset
Reaction
Time
t
Reset Delay Time
During power−up (or restoring OUT voltage from a reset
event), the OUT voltage must be maintained above the Reset
threshold for the Reset Delay time before RO goes high. The
time for Reset Delay is determined by the choice of IC and
the state of the DT pin.
Reset Delay Time Select
Selection of the NCV8660C device and the state of the DT
pin determines the available Reset Delay times. The part is
designed for use with DT tied to ground or OUT, but may be
controlled by any logic signal which provides a threshold
between 0.8 V and 2 V. The default condition for an open DT
pin is the faster Reset time (DT = GND condition). Times are
in pairs and are highlighted in the chart below. Consult
factory for availability.
NCV86601C
NCV86602C
NCV86603C
NCV86604C
DT=GND
Reset Time
8 ms
8 ms
16 ms
32 ms
DT=OUT
Reset Time
128 ms
32 ms
64 ms
128 ms
NOTE: The timing values can be selected from the
following list: 8, 16, 32, 64, 128 ms. Contact factory for
options not included in ORDERING INFORMATION table
on page 10.
The Delay Time select (DT) pin is logic level controlled
and provides Reset Delay time per the chart. Note the DT pin
is sampled only when RO is low, and changes to the DT pin
when RO is high will not effect the reset delay time.
Thermal Shutdown
When the die temperature exceeds the Thermal Shutdown
threshold, a Thermal Shutdown event is detected OUT is
turned off, and RO goes low. The IC will remain in this state
until the die temperature moves below the shutdown
threshold (175°C typical) minus the hysteresis factor (25°C
typical). The output will then turn back on and RO will go
high after the RESET Delay time.
Hints
For better EMC performance on RO and DT pins is
recommended to use additional decoupling 100 pF ceramic
capacitors connected between DT pin and GND and RO pin
and GND, respectively. Capacitors should be placed as near
as possible to the corresponding pin and the connection
between capacitor ground pad and system GND pin should
be as short as possible.
Input Capacitor CIN is required if regulator is located far
from power supply filter. If extremely fast input voltage
transients are expected with slew rate in excess of 4 V/ms
then appropriate input filter must be used. The filter can be
composed of several capacitors in parallel.
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