7585AILZ データシートの表示（PDF） - Renesas Electronics

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7585AILZ

TFT-LCD Power Supply

Renesas Electronics 

EL7585A

Over-Temperature Protection

An internal temperature sensor continuously monitors the die

temperature. In the event that the die temperature exceeds the

thermal trip point of 140°C, the device will shut down.

Layout Recommendation

The device's performance including efficiency, output noise,

transient response and control loop stability is dramatically

affected by the PCB layout. PCB layout is critical, especially at

high switching frequency.

There are some general guidelines for layout:

1. Place the external power components (the input capacitors,

output capacitors, boost inductor and output diodes, etc.) in

close proximity to the device. Traces to these components

should be kept as short and wide as possible to minimize

parasitic inductance and resistance.

2. Place VREF and VDD bypass capacitors close to the pins.

3. Minimize the length of traces carrying fast signals and high

current.

4. All feedback networks should sense the output voltage

directly from the point of load, and be as far away from LX

node as possible.

5. The power ground (PGND) and signal ground (SGND) pins

should be connected at only one point near the main

decoupling capacitors.

6. The exposed die plate, on the underneath of the package,

should be soldered to an equivalent area of metal on the

PCB. This contact area should have multiple via

connections to the back of the PCB as well as connections

to intermediate PCB layers, if available, to maximize

thermal dissipation away from the IC.

7. To minimize the thermal resistance of the package when

soldered to a multi-layer PCB, the amount of copper track

and ground plane area connected to the exposed die plate

should be maximized and spread out as far as possible

from the IC. The bottom and top PCB areas especially

should be maximized to allow thermal dissipation to the

surrounding air.

8. A signal ground plane, separate from the power ground

plane and connected to the power ground pins only at the

exposed die plate, should be used for ground return

connections for feedback resistor networks (R1, R11, R41)

and the VREF capacitor, C22, the CDELAY capacitor C7 and

the integrator capacitor C23.

9. Minimize feedback input track lengths to avoid switching

noise pick-up.

A two-layer demo board is available to illustrate the proper

layout implementation. A four-layer demo board can be used to

further optimize the layout recommendations.

Demo Board Layout

FIGURE 27. TOP LAYER

FN7523 Rev 3.00

March 9, 2006

FIGURE 28. BOTTOM LAYER

Page 17 of 19

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