7585AILZ データシートの表示（PDF） - Renesas Electronics

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7585AILZ

TFT-LCD Power Supply

Renesas Electronics 

EL7585A

EL7585A

The following equation gives the boundary between

discontinuous and continuous boost operation. For

continuous operation (LX switching every clock cycle) we

require that:

I(AVDD_load) > D*(1-D)*VIN/(2*L*FOSC)

where the duty cycle, D = (AVDD - VIN)/AVDD

For example, with VIN = 5V, FOSC = 1.0MHz and AVDD =

12V we find continuous operation of the boost converter can

be guaranteed for:

L = 10µH and I(AVDD) > 61mA

L = 6.8µH and I(AVDD) > 89mA

L = 3.3µH and I(AVDD) > 184mA

Charge Pump Output Capacitors

Ceramic capacitors with low ESR are recommended. With

ceramic capacitors, the output ripple voltage is dominated by

the capacitance value. The capacitance value can be

chosen by the following equation:

COUT  2----------V----R-----I-P-I--O-P---U-L----ET---------f--O-----S----C--

where fOSC is the switching frequency.

Start-Up Sequence

Figure 26 shows a detailed start-up sequence waveform. For

a successful power-up, there should be six peaks at VCDLY.

When a fault is detected, the device will latch off until either

EN is toggled or the input supply is recycled.

When the input voltage (VDD) exceeds 2.5V, VREF and

VLOGIC turn on. At the same time, if EN is tied to VDD, an

internal current source starts to charge CDLY to an upper

threshold using a fast ramp followed by a slow ramp. If EN is

low at this point, the CDLY ramp will be delayed until EN

goes high.

The first four ramps on CDLY (two up, two down) are used to

initialize the fault protection switch and to check whether

there is a fault condition on CDLY or VREF. If a fault is

detected, the outputs and the input protection will turn off,

but VREF will stay on. If no fault is found, CCDLY continues

ramping up and down.

During the second ramp, the device checks the status of

VREF and over temperature. At the peak of the second ramp,

PG output goes low and enables the input protection PMOS

Q1. Q1 is a controlled FET used to prevent in-rush current into

VBOOST before VBOOST is enabled internally. Its rate of turn

on is controlled by Co. When a fault is detected, M1 will turn

off and disconnect the inductor from VIN.

With the input protection FET on, NODE1 (See Typical

Application Diagram) will rise to ~VIN. Initially the boost is not

enabled so VBOOST rises to VIN-VDIODE through the output

diode. Hence, there is a step at VBOOST during this part of the

start-up sequence. If this step is not desirable, an external

PMOS FET can be used to delay the output until the boost is

enabled internally. The delayed output appears at AVDD.

For EL7585A, VBOOST soft-start at the beginning of the third

ramp. The soft-start ramp depends on the value of the CDLY

capacitor. For CDLY of 220nF, the soft-start time is ~2ms.

VOFF turns on at the start of the fourth peak. At the fifth

peak, the open drain o/p DELB goes low to turn on the

external PMOS Q4 to generate a delayed VBOOST output.

VON is enabled at the beginning of the sixth ramp. AVDD,

PG, VOFF, DELB and VON are checked at end of this ramp.

Fault Protection

During the startup sequence, prior to BOOST soft-start,

VREF is checked to be within ±20% of its final value and the

device temperature is checked. If either of these are not

within the expected range, the part is disabled until the

power is recycled or EN is toggled.

If CDELAY is shorted low, then the sequence will not start,

while if CDELAY is shorted H, the first down ramp will not

occur and the sequence will not complete.

Once the start-up sequence is completed, the chip

continuously monitors CDLY, DELB, FBP, FBL, FBN, VREF,

FBB and PG and checks for faults. During this time, the

voltage on the CDLY capacitor remains at 1.15V until either a

fault is detected, or the EN pin is pulled low.

A fault on CDELAY, VREF or temperature will shut down the

chip immediately. If a fault on any other output is detected,

CDELAY will ramp up linearly with a 5µA (typical) current to

the upper fault threshold (typically 2.4V), at which point the

chip is disabled until the power is recycled or EN is toggled.

If the fault condition is removed prior to the end of the ramp,

the voltage on the CDLY capacitor returns to 1.15V.

Typical fault thresholds for FBP, FBL, FBN and FBB are

included in the tables. PG and DELB fault thresholds are

typically 0.6V.

CINT has an internal current-limited clamp to keep the

voltage within its normal range. If CINT is shorted low, the

boost regulator will attempt to regulate to 0V. If CINT is

shorted H, the regulator switches to P mode.

If any of the regulated outputs (VBOOST, VON, VOFF or

VLOGIC) are driven above their target levels the drive

circuitry will switch off until the output returns to its expected

value.

If VBOOST is excessively loaded, the current limit will

prevent damage to the chip. While in current limit, the part

acts like a current source and the regulated output will drop.

If the output drops below the fault threshold, a ramp will be

initiated on CDELAY and, provided that the fault is sustained,

the chip will be disabled on completion of the ramp.

FN7523 Rev 3.00

March 9, 2006

Page 14 of 19

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