W78E51B データシートの表示（PDF） - Winbond
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コンポーネント説明
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W78E51B Datasheet PDF : 23 Pages
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Preliminary W78E51B
BLOCK DIAGRAM
P1.0
~
Port
P1.7
1
Port 1
Latch
INT2
INT3
Interrupt
P3.0
~
P3.7
Timer
0
Timer
1
UART
Port
Port 3
3
Latch
ACC
T1
B
T2
PSW
Stack
ALU
Pointer
Instruction
Decoder
&
Sequencer
SFR RAM
Address
128 bytes
RAM & SFR
Port 0
Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
P4.0
~
P4.3
Port
4
Port 4
Latch
Bus & Clock
Controller
ROM
Watchdog
Timer
Oscillator
Reset Block Power control
Port 2
Latch
XTAL1 XTAL2 ALE PSEN RST
Vcc
Vss
P0.0
Port
0
~
P0.7
Port
2
P2.0
~
P2.7
FUNCTIONAL DESCRIPTION
The W78E51B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
-4-
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