IDT54FCT88915TT133L データシートの表示（PDF） - Integrated Device Technology
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IDT54FCT88915TT133L Datasheet PDF : 11 Pages
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
tRISE/FALL
All outputs
tPULSE WIDTH (3)
All outputs(3)
Parameter
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4, Q5, Q/2, 2Q @ 1.5V
Condition(1)
Load = 50Ω to
VCC/2, CL = 20pF
Min.
0.2(2)
0.5tCYCLE – 0.5(5)
Max.
1.2
0.5tCYCLE + 0.5(5)
Unit
ns
ns
tPD
SYNC input to FEEDBACK delay
SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK
input pins)
Load = 50Ω to
VCC/2, CL = 20pF
0.1µF from LF to
Analog GND(9)
–0.5
+0.5
ns
tSKEWr
(rising)(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
Load = 50Ω to
—
VCC/2, CL = 20pF
350
ps
tSKEWf
(falling)(3,4)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
—
350
ps
tSKEWall (3,4)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
—
500
ps
tLOCK (6)
Time required to acquire
1(2)
10
ms
Phase-Lock from time
SYNC input signal is received
tPZH
Output Enable Time
tPZL
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
3(2)
14
ns
tPHZ
Output Disable Time
3(2)
14
ns
tPLZ
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
GENERAL AC SPECIFICATION NOTES:
3072 tbl 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions, and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF.
(Where C1 is loop filter capacitor shown in Figure 1).
9.7
5
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