507M-01 データシートの表示（PDF） - Integrated Device Technology
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507M-01 Datasheet PDF : 7 Pages
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ICS507-01
PECL CLOCK SYNTHESIZER
PECL MULTIPLIER
Pin Assignment
X1/ICLK 1
VDD 2
VDD 3
S1 4
GND 5
GND 6
NC 7
PECL 8
16 X2
15 NC
14 S0
13 OE
12 NC
11 NC
10 RES
9 PECL
16 Pin (150 mil) SOIC
* At 3.3V, use this selection to get 155.52 MHz from a
16 MHz input.
For lowest phase noise generation of 155.52 MHz, use
a 19.44 MHz crystal and the 8X selection.
Pin Descriptions
Clock Multiplier Select Table
S1 S0 Multiplier
00
9.72X*
0M
10X
01
12X
M0
6.25X
MM
8X
M1
5X
10
2X
1M
3X
11
4X
0 = connect pin directly to ground
1 = connect pin directly to VDD
M = leave unconnected (floating)
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
XI/ICLK
VDD
VDD
S1
GND
GND
NC
PECL
PECL
RES
NC
NC
OE
S0
NC
X2
Type
Description
Input Crystal Connection. Connect to a fundamental parallel mode crystal, or
clock.
Power Connect to +3.3 V or 5 V, and to VDD on pin 3.
Power Connect to VDD on pin 2. Decouple with pin 5.
Input Multiplier select pin 1. Determines output frequency per table above.
Power Connect to ground.
Power Connect to ground.
— No connect. Do not connect this pin to anything.
Output PECL output. Connect to resistor load as shown on page 1.
Output Complimentary PECL output. Connect to resistor load as shown on
page 1.
Input Bias resistor input. Connect a resistor between this pin and VDD.
— No connect. Do not connect this pin to anything.
— No connect. Do not connect this pin to anything.
Input Output Enable. Tri-states both outputs when low. Internal pull-up.
Input Multiplier select pin 0. Determines output frequency per table above.
— No connect. Do not connect this pin to anything.
Output Crystal Connection. Connect to crystal, or leave unconnected for clock
input.
IDT™ / ICS™ PECL CLOCK SYNTHESIZER
2
ICS507-01
REV I 041905
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