IDT5P49V5901 データシートの表示（PDF） - Integrated Device Technology

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IDT5P49V5901

PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5P49V5901

PROGRAMMABLE CLOCK GENERATOR

CLOCK SYNTHESIZER

Table 22: PCI Express Jitter Specifications (VDDO = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

Symbol

Parameter

Conditions

Min Typ Max PCIe Industry Units Notes

Specification

tJ

(PCIe Gen1)

Phase Jitter

Peak-to-Peak

ƒ= 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

30

86

ps

1,4

tREFCLK_HF_RMS

ƒ= 100MHz, 25MHz Crystal Input

(PCIe Gen2) Phase Jitter RMS High Band: 1.5MHz - Nyquist (clock

frequency/2)

2.56

3.10

ps

2,4

tREFCLK_LF_RMS

(PCIe Gen2)

Phase Jitter RMS

ƒ= 100MHz, 25MHz Crystal Input

Low Band: 10kHz - 1.5MHz

0.27

3.0

ps

2,4

tREFCLK_RMS

ƒ= 100MHz, 25MHz Crystal Input

0.8

(PCIe Gen3) Phase Jitter RMS Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

1.0

ps

3,4

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.

2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting

the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High

Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).

3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the

PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is subject to change pending the final release version of the specification.

4. This parameter is guaranteed by characterization. Not tested in production.

Table 23: Spread Spectrum Generation Specifications

Symbol Parameter

Description

fOUT

fMOD

fSPREAD

Output Frequency Output Frequency Range

Mod Frequency Modulation Frequency

Spread Value

Amount of Spread Value (programmable) - Center Spread

Amount of Spread Value (programmable) - Down Spread

Min Typ Max

5

300

30 to 63

±0.25% to ±2.5%

-0.5% to -5%

Unit

MHz

kHz

%fOUT

IDT® PROGRAMMABLE CLOCK GENERATOR

18

IDT5P49V5901

REV A 031014

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