IDT5P49V5901 データシートの表示（PDF） - Integrated Device Technology
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IDT5P49V5901 Datasheet PDF : 35 Pages
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IDT5P49V5901
PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Symbol
Parameter
Test Conditions
Min. Typ. Max.
t6 Clock Jitter
Cycle-to-Cycle jitter (Peak-to-Peak), multiple
46
output frequencies switching, differential
outputs (1.8V to 3.3V nominal output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
Cycle-to-Cycle jitter (Peak-to-Peak), multiple
74
output frequencies switching, LVCMOS
outputs (1.8 to 3.3V nominal output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 5MHz
0.5
integration range) reference clock (OUT0),
25 MHz LVCMOS outputs (1.8 to 3.3V
nominal output voltage).
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 20MHz
integration range) differential output, VDDO =
3.465V, 25MHz crystal, 156.25MHz output
frequency
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
0.75 1.5
t7 Output Skew
t8 3 Lock Time
t9 4 Lock Time
Skew between the same frequencies, with
outputs using the same driver format and
phase delay set to 0ns.
PLL lock time from power-up
PLL lock time from shutdown mode
75
10
20
2
1. Practical lower frequency is determined by loop filter settings.
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from memory to PLL registers. It does not include memory programming/write time.
4. Actual PLL lock time depends on the loop configuration.
Units
ps
ps
ps
ps
ps
ms
ms
IDT® PROGRAMMABLE CLOCK GENERATOR
17
IDT5P49V5901
REV A 031014
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