CY7C1329_04 データシートの表示（PDF） - Cypress Semiconductor
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CY7C1329_04 Datasheet PDF : 15 Pages
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CY7C1329
Capacitance[9]
Parameter
CIN
CCLK
CI/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
Max.
Unit
4
pF
4
pF
4
pF
AC Test Loads and Waveforms
OUTPUT
3.3V
Z0 = 50Ω
OUTPUT
RL = 50Ω
5 pF
VL = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
R = 317Ω
3.3V
10%
GND
R = 351Ω
< 3.3 ns
ALL INPUT PULSES[10]
90%
90%
10%
< 3.3 ns
(b)
(c)
Switching Characteristics Over the Operating Range[11,12,13]
-133
-100
Parameter
Description
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
1.9
3.2
ns
tCL
Clock LOW
1.9
3.2
ns
tAS
Address Set-up Before CLK Rise
1.5
2.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tCO
Data Output Valid After CLK Rise
4.2
5.0
ns
tDOH
Data Output Hold After CLK Rise
1.5
2.0
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.5
2.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
tWES
BWE, GW, BW[3:0] Set-up Before CLK Rise
1.5
2.5
ns
tWEH
BWE, GW, BW[3:0] Hold After CLK Rise
0.5
0.5
ns
tADVS
ADV Set-up Before CLK Rise
1.5
2.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
tDS
Data Input Set-up Before CLK Rise
1.5
2.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCES
Chip Select Set-up
1.5
2.5
ns
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
tEOV
Chip Select Hold After CLK Rise
Clock to High-Z[12]
Clock to Low-Z[12]
OE HIGH to Output High-Z[12, 13]
OE LOW to Output Low-Z[12, 13]
OE LOW to Output Valid[12]
0.5
0.5
ns
1.5
3.5
1.5
5
ns
0
0
ns
3.5
5.5
ns
0
0
ns
4.2
5.0
ns
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Input waveform should have a slew rate of 1V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
Document #: 38-05279 Rev. *B
Page 8 of 15
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