LTC6820 データシートの表示（PDF） - Linear Technology
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LTC6820 Datasheet PDF : 28 Pages
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LTC6820
Electrical Characteristics The l denotes the specifications which apply over the full specified
junction temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, VDDS = 1.7V to 5.5V, RBIAS = 2k to 20k
unless otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
ILEAK(DIG) Digital Pin Input Leakage Current
CI/O
Input/Output Pin Capacitance
Isolated Pulse Timing (See Figure 2)
PHA, POL, MSTR, SLOW = 0V to VDD
l
CS, SCK, MOSI, MISO, EN = 0V to VDDS
(Note 9)
±1
µA
10
pF
t1/2PW(CS) Chip-Select Half-Pulse Width
tINV(CS) Chip-Select Pulse Inversion Delay
tDEL(CS) Chip-Select Response Delay
t½PW(D) Data Half-Pulse Width
tINV(D) Data Pulse Inversion Delay
tDEL(D) Data Response Delay
isoSPI™ Timing—Master (See Figures 3, 4)
(Note 8)
l 120
150
180
ns
l
200
ns
l
140
190
ns
l 40
50
60
ns
l
70
ns
l
75
120
ns
tCLK
SCK Latching Edge to SCK Latching Edge (Note 7)
SLOW = 0 l 1
µs
SLOW = 1 l 5
µs
t1
MOSI Setup Time Before SCK Latching Edge
t2
MOSI Hold Time After SCK Latching Edge
t3
SCK Low
t4
SCK High
t5
CS Rising Edge to CS Falling Edge
t6
SCK Latching Edge to CS Rising Edge
t7
CS Falling Edge to SCK Latch Edge
t8
SCK Non-Latch Edge to MISO Valid
t9
SCK Latching Edge to Short ±1 Transmit
t10
CS Transition to Long ±1 Transmit
t11
CS Rising Edge to MISO Rising
isoSPI Timing—Slave (See Figures 3, 4)
(Note 8)
tCLK = t3 + t4 ≥ 1µs
tCLK = t3 + t4 ≥ 1µs
(Note 7)
(Note 7)
(Note 8)
(Note 8)
l 25
l 25
l 50
l 50
l 0.6
l
1
l
1
l
l
l
l
ns
ns
ns
ns
µs
µs
µs
55
ns
50
ns
55
ns
55
ns
t12
isoSPI Data Recognized to SCK
Latching Edge
(Note 8)
SLOW = 0 l 110
145
185
ns
SLOW = 1 l 0.9
1.1
1.4
µs
t13
SCK Pulse Width
SLOW = 0 l 90
115
150
ns
SLOW = 1 l 0.9
1.1
1.4
µs
t14
SCK Non-Latch Edge to isoSPI Data Transmit (Note 8)
SLOW = 0 l 115
145
190
ns
SLOW = 1 l 0.9
1.1
1.4
µs
t15
CS Falling Edge to SCK Non-Latch Edge
PHA = 1
SLOW = 0 l 90
120
160
ns
SLOW = 1 l 0.9
1.1
1.4
µs
t16
CS Falling Edge to isoSPI Data Transmit
SLOW = 0 l 200
265
345
ns
SLOW = 1 l 1.8
2.2
2.8
µs
t17
CS Rising Edge to SCK Latching Edge
PHA = 1
SLOW = 0 l 90
120
160
ns
SLOW = 1 l 0.9
1.1
1.4
µs
t18
CS Rising Edge to MOSI Rising Edge
tRTN
Data Return Delay
l
SLOW = 0 l
SLOW = 1 l
35
ns
485
625
ns
3.3
4
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, and all voltages are referenced
to GND unless otherwise specified.
4
Note 3: The LTC6820I is guaranteed to meet specified performance
from –40°C to 85°C. The LTC6820H is guaranteed to meet specified
performance from –40°C to 125°C.
Note 4: Active supply current (IDD) is dependent on the amount of time
that the output drivers are active on IP and IM. During those times IDD will
increase by the 20 • IB drive current. For the maximum data rate 1MHz,
the drivers are active approximately 10% of the time if MSTR = 1, and 5%
6820f
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