LTC6820 データシートの表示（PDF） - Linear Technology
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LTC6820 Datasheet PDF : 28 Pages
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LTC6820
Electrical Characteristics The l denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, VDDS = 1.7V to 5.5V, RBIAS = 2k to 20k unless
otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
Power Supply
VDD
Operating Supply Voltage Range
VDDS
IO Supply Voltage Range (Level Shifting)
IDD
Supply Current, READY/ACTIVE States
(Note 4)
Supply Current, IDLE State
IDDS
IO Supply Current (Note 5)
Biasing
VBIAS
Voltage on IBIAS Pin
IB
Isolated Interface Bias Current (Note 6)
AIB
Isolated Interface Current Gain
VA
Transmitter Pulse Amplitude
VICMP Threshold-Setting Voltage on ICMP Pin
ILEAK(ICMP) Leakage Current on ICMP Pin
ILEAK(IP/IM) Leakage Current on IP and IM Pins
ATCMP
Receiver Comparator Threshold Voltage
Gain
VCM
Receiver Common Mode Bias
RIN
Receiver Input Resistance
Idle/Wake-Up (See Figures 13, 14, 15)
VWAKE
Differential Wake-Up Voltage
(See Figure 13)
tDWELL Dwell Time at VWAKE
tREADY Start-Up Time After Wake Detection
tIDLE
Idle Time-Out Duration
Digital I/O
VIH(CFG) Digital Voltage Input High, Configuration
Pins (PHA, POL, MSTR, SLOW)
VIL(CFG) Digital Voltage Input Low, Configuration
Pins (PHA, POL, MSTR, SLOW)
VIH(SPI) Digital Voltage Input High, SPI Pins
(CS, SCK, MOSI, MISO)
VIL(SPI) Digital Voltage Input Low, SPI Pins
(CS, SCK, MOSI, MISO)
VIH(EN) Digital Voltage Input High, EN Pin
VIL(EN) Digital Voltage Input Low, EN Pin
VOH
Digital Voltage Output High (CS and SCK)
VOL
Digital Voltage Output Low
(MOSI, MISO, CS, SCK)
CONDITIONS
MIN
TYP
MAX UNITS
l 2.7
5.5
V
Affects CS, SCK, MOSI, MISO and EN Pins l 1.7
5.5
V
RBIAS = 2kΩ (IB = 1mA)
1/tCLK = 0MHz l
4
4.8
5.8
mA
1/tCLK = 1MHz
7
mA
RBIAS = 20kΩ (IB = 0.1mA) 1/tCLK = 0MHz l 1.3
2
1/tCLK = 1MHz
2.4
2.9 mA
mA
MSTR = 0V
l
2
6
µA
MSTR = VDD
l
1
3
µA
SPI Inputs and EN Pin at 0V or VDDS,
l
SPI Outputs Unloaded
1
µA
READY/ACTIVE State
l
IDLE State
RBIAS = 2k to 20k
VA ≤ 1.6V
l
IB = 1mA l
IB = 0.1mA l
VA = |VIP – VIM|
VDD < 3.3V l
VDD ≥ 3.3V l
VTCMP = ATCMP • VICMP
l
VICMP = 0V to VDD
l
IDLE State, VIP = VIM = 0V to VDD
l
VCM = VDD/2 to VDD – 0.2V,
l
VICMP = 0.2V to 1.5V
IP/IM Not Driving
Single-Ended to IP or IM
l
1.9
2.0
2.1
V
0
V
VBIAS/RBIAS
18
20
22
18
20
24
mA
mA/mA
mA/mA
VDD – 1.7V
V
1.6
V
0.2
1.5
V
±1
µA
±2
µA
0.4
0.5
0.6
V/V
(VDD – VICMP/3 – 167mV)
V
26
35
42
kΩ
tDWELL = 240ns
VWAKE = 240mV
l 240
mV
l 240
ns
l
8
µs
l
4
5.7
7.5
ms
VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW) l 0.7 • VDD
VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW) l
VDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 3.3V, Sourcing 2mA
VDDS = 1.7V, Sourcing 1mA
VDDS = 3.3V, Sinking 3.3mA
VDDS = 1.7V, Sinking 1mA
l 0.7 • VDDS
l 0.8 • VDDS
l
l
l
2
l 0.85 • VDDS
l
l
l VDDS – 0.2
l VDDS – 0.25
l
l
V
0.3 • VDD
V
V
V
0.3 • VDDS
V
0.2 • VDDS
V
V
V
0.8
V
0.25 • VDDS
V
V
V
0.2
V
0.2
V
6820f
3
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