UPD720102 データシートの表示（PDF） - NEC => Renesas Technology

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UPD720102

USB 2.0 HOST CONTROLLER

NEC => Renesas Technology 

μPD720102

PCI Bus Interface

Arbiter

OHCI Host Controller

EHCI Host Controller

Root Hub

PHY

INTA0

SMI0

PME0

: handles 32-bit 33 MHz PCI bus master and target function which comply with PCI

specification revision 2.2. The number of enabled ports is set by bit in configuration

space.

: arbitrates among two OHCI host controller cores and one EHCI host controller core.

: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling.

: handles high- (480 Mbps) signaling.

: handles USB hub function in host controller and controls connection (routing) between

host controller core and port.

: consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,

etc.

: is the PCI interrupt signal for OHCI Host Controller.

: is the interrupt signal which is specified by open host controller interface specification

for USB release 1.0a and enhanced host controller interface specification revision 1.0.

The SMI signal of each OHCI host controller and EHCI host controller appears at this

signal.

: is the interrupt signal which is specified by PCI-bus power management interface

specification revision 1.1. Wakeup signal of each host controller core appears at this

signal.

Data Sheet S17998EJ4V0DS

3

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