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UPD720101 データシートの表示(PDF) - NEC => Renesas Technology

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UPD720101
NEC
NEC => Renesas Technology NEC
UPD720101 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
µPD720101
Pin Name
SMC
TEB
AMC
TEST
NANDTEST
AVDD
VDD
VDD_PCI
AVSS
VSS
N.C.
I/O
Buffer Type
Active
Level
Function
I
Input with 50 kpull down R High
Scan mode control
I
Input with 50 kpull down R High
BIST enable
I
Input with 50 kpull down R High
ATG mode control
I
Input with 50 kpull down R High
Test control
I
Input with 50 kpull down R High
NAND tree test enable
VDD for analog circuit
VDD
5 V (5 V PCI) or 3.3 V (3.3 V PCI)
VSS for analog circuit
VSS
No connection
(2/2)
Remarks 1. “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
2. “5 V PCI” indicates a PCI buffer, which complies with the 3 V PCI standard, has a 5 V tolerant circuit. It
does not indicate that this buffer fully complies with 5 V PCI standard. However, this function can be
used for evaluating the operation of a device on a 5 V add-in card.
3. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they
do not need to be considered in normal use.
Data Sheet S16265EJ4V0DS
9

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