UPD720101 データシートの表示（PDF） - NEC => Renesas Technology

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UPD720101

USB2.0 HOST CONTROLLER

NEC => Renesas Technology 

µPD720101

PCI Bus Interface

Arbiter

OHCI Host Controller #1

OHCI Host Controller #2

EHCI Host Controller

Root Hub

PHY

INTA0

INTB0

INTC0

SMI0

PME0

: handles 32-bit 33 MHz PCI bus master and target function which comply with PCI

specification release 2.2. The number of enabled ports is set by bit in configuration

space.

: arbitrates among two OHCI host controller cores and one EHCI host controller core.

: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.

: handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.

: handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.

: handles USB hub function in host controller and controls connection (routing) between

host controller core and port.

: consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,

etc.

: is the PCI interrupt signal for OHCI Host Controller #1.

: is the PCI interrupt signal for OHCI Host Controller #2.

: is the PCI interrupt signal for EHCI Host Controller.

: is the interrupt signal which is specified by Open Host Controller Interface Specification

for USB Rev 1.0a and Enhanced Host Controller Interface Specification Rev 1.0. The

SMI signal of each OHCI Host Controller and EHCI Host Controller appears at this

signal.

: is the interrupt signal which is specified by PCI-Bus Power Management Interface

Specification release 1.1. Wakeup signal of each host controller core appears at this

signal.

COMPARISON WITH THE µPD720100A

EHCI revision

EHCI

OHCI

Legacy support

Clock

Package

µPD720100A

0.95

1

2

Parallel IRQ out support

48 MHz OSC or 30 MHz OSC/X’tal

176-pin BGA (FP) or 160-pin LQFP

µPD720101 (2nd generation)

1.0

1

2

No parallel IRQ support

48 MHz OSC or 30 MHz X’tal

144-pin BGA (FP) or 144-pin LQFP

Data Sheet S16265EJ4V0DS

3

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